Abstract: The present invention related to self-limiting filters, arrays of such filters, and methods thereof. In particular embodiments, the filters include a metal transition film (e.g., a VO2 film) capable of undergoing a phase transition that modifies the film's resistivity. Arrays of such filters could allow for band-selective interferer rejection, while permitting transmission of non-interferer signals.

Abstract: An embodiment of the present disclosure is directed to a semiconductor device. The semiconductor devise comprises a substrate. An epitaxially grown semiconductor material is disposed over at least a portion of the substrate. A nanotemplate structure is disposed at least partially within the semiconductor material. The nanotemplate structure comprises a plurality of dielectric nanoscale features defining a plurality of nanoscale windows. An air gap is disposed between at least a portion of one or more of the nanoscale features and the semiconductor material.

Abstract: Lattice-mismatched semiconductor devices having a substrate, a first epitaxial film disposed thereon, a dielectric material, and a second epitaxial film. The first epitaxial film contains etch pits that extend from the outer surface of the first epitaxial film into the first epitaxial film. The dielectric material is disposed within the etch pits and blocks at least some of the threading dislocations in the first epitaxial film from propagating into the second epitaxial film. Semiconductor devices containing a silicon (Si) substrate or a silicon germanium (SiGe) substrate, a germanium (Ge) film disposed over the substrate, and a dielectric material. Methods for producing such semiconductor devices.

Abstract: An embodiment of the present disclosure is directed to a semiconductor device. The semiconductor devise comprises a substrate. An epitaxially grown semiconductor material is disposed over at least a portion of the substrate. A nanotemplate structure is disposed at least partially within the semiconductor material. The nanotemplate structure comprises a plurality of dielectric nanoscale features defining a plurality of nanoscale windows. An air gap is disposed between at least a portion of one or more of the nanoscale features and the semiconductor material.

Abstract: An embodiment of the present disclosure is directed to a semiconductor device. The semiconductor devise comprises a substrate. An epitaxially grown semiconductor material is disposed over at least a portion of the substrate. A nanotemplate structure is disposed at least partially within the semiconductor material. The nanotemplate structure comprises a plurality of dielectric nanoscale features defining a plurality of nanoscale windows. An air gap is disposed between at least a portion of one or more of the nanoscale features and the semiconductor material.

Abstract: An exemplary embodiment of the present invention is a photodetector comprising a semiconductor body, a periodically patterned metal nanoantenna disposed on a surface of the semiconductor body, and at least one electrode separate from the nanoantenna. The semiconductor body comprises an active layer in sufficient proximity to the nanoantenna for plasmonic coupling thereto. The nanoantenna is dimensioned to absorb electromagnetic radiation in at least some wavelengths not more than 12 ?m that are effective for plasmonic coupling into the active layer. The electrode is part of an electrode arrangement for obtaining a photovoltage or photocurrent in operation under appropriate stimulation.

Abstract: Exemplary embodiments provide methods for planarizing a semiconductor surface. In embodiments, the disclosed planarizing methods can include a chemical mechanical planarization (CMP) process using a slurry-free solution that includes hydrogen peroxide (H2O2) but is free of particles such as oxide particles. A semiconductor surface (e.g., germanium) can then be planarized to provide a desirable surface roughness. In embodiments, high-quality Group III-V materials can be formed on the planarized semiconductor surface.

Abstract: Exemplary embodiments provide methods of forming semiconductor devices, by which defects formed upon nucleation and coalescence of semiconductor islands can be reduced or eliminated. In one embodiment, an annealing process can be performed prior to coalescence of the semiconductor islands into a continuous semiconductor layer. In another embodiment, high-quality Group III-V materials can be formed on the continuous semiconductor layer.