Patents by Inventor Darlene G. Hamilton
Darlene G. Hamilton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8938655Abstract: Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate.Type: GrantFiled: December 20, 2007Date of Patent: January 20, 2015Assignee: Spansion LLCInventors: Darlene G. Hamilton, Mark W. Randolph, Don Carlos Darling, Ron Kornitz
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Patent number: 7652919Abstract: The claimed subject matter provides systems and/or methods that facilitate programming and reading multi-level, multi-bit memory cells in a memory device. In multi-bit memory cells, programming one element can affect the second element. Certain combinations of elements can cause excessive levels of complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb, reducing memory device reliability. Such effects may be pronounced where a high charge level is programmed into a first element while a second element of the same memory cell is unprogrammed. Memory cell elements can be programmed using additional charge levels to mitigate such effects.Type: GrantFiled: June 29, 2007Date of Patent: January 26, 2010Assignee: Spansion LLCInventors: Darlene G. Hamilton, Kulachet Tanpairoj, Fatima Bathul, Ou Li
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Patent number: 7626869Abstract: Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.Type: GrantFiled: May 7, 2007Date of Patent: December 1, 2009Assignee: Spansion LLCInventors: Xuguang Wang, Yi He, Zhizheng Liu, Sung-Yong Chung, Darlene G. Hamilton, Ashot Melik-Martirosian, Gulzar Kathawala, Ming Sang Kwan, Mark Randolph, Timothy Thurgate
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Publication number: 20090161466Abstract: Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Applicant: SPANSION LLCInventors: Darlene G. Hamilton, Mark W. Randolph, Don Carlos Darling, Ron Kornitz
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Publication number: 20080279014Abstract: Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.Type: ApplicationFiled: May 7, 2007Publication date: November 13, 2008Applicant: SPANSION LLCInventors: Xuguang Wang, Yi He, Zhizheng Liu, Sung-Yong Chung, Darlene G. Hamilton, Ashot Melik-Martirosian, Gulzar Kathawala, Ming Sang Kwan, Mark Randolph, Timothy Thurgate
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Publication number: 20080158954Abstract: The claimed subject matter provides systems and/or methods that facilitate programming and reading multi-level, multi-bit memory cells in a memory device. In multi-bit memory cells, programming one element can affect the second element. Certain combinations of elements can cause excessive levels of complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb, reducing memory device reliability. Such effects may be pronounced where a high charge level is programmed into a first element while a second element of the same memory cell is unprogrammed. Memory cell elements can be programmed using additional charge levels to mitigate such effects.Type: ApplicationFiled: June 29, 2007Publication date: July 3, 2008Applicant: SPANSION LLCInventors: Darlene G. Hamilton, Fatima Bathul, Kulachet Tanpairoj, Ou Li
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Patent number: 7103706Abstract: A system and methodology is provided for proper reading of multi-bit memory cells in a memory device. A first reference cell and a second reference cell is employed to determine an average dynamic reference value. The average dynamic reference value is determined by reading a programmed bit of the first reference cell and reading an unprogrammed or erased bit of a second reference cell to determine an average dynamic reference value. The average dynamic reference value can be utilized to determine whether data cells are in a programmed state or in an unprogrammed state.Type: GrantFiled: September 3, 2004Date of Patent: September 5, 2006Assignee: Spansion LLCInventors: Michael A. Van Buskirk, Darlene G. Hamilton, Pua-Ling Chen, Kazuhiro Kuribara
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Patent number: 7023740Abstract: A method and system for substrate bias for programming non-volatile memory. A bias voltage is applied to a deep well structure under a well comprising a channel region for a non-volatile memory cell. During programming, a negative bias applied to the deep well beneficially creates a non-uniform distribution of electrons within the channel region, with an abundance of electrons at the surface of the channel region. The application of additional bias voltages to a control gate and a drain may cause electrons to migrate from the channel region to a storage layer of the non-volatile memory cell. Advantageously, due to the increased supply of electrons at the surface of the channel region, programming of the non-volatile cell takes place faster than under the conventional art.Type: GrantFiled: January 12, 2004Date of Patent: April 4, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Nga-Ching Wong, Darlene G. Hamilton
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Patent number: 7010736Abstract: An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.Type: GrantFiled: July 22, 2002Date of Patent: March 7, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Boon Tang Teh, Edward V. Bautista, Jr., Ken Cheong Cheah, Colin Bill, Joseph Kucera, Weng Fook Lee, Darlene G. Hamilton
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Patent number: 6967873Abstract: A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.Type: GrantFiled: October 2, 2003Date of Patent: November 22, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Darlene G. Hamilton, Zhizheng Liu, Mark W. Randolph, Yi He, Edward Hsia, Kulachet Tanpairoj, Mimi Lee, Alykhan Madhani
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Patent number: 6956768Abstract: A method of programming a multi-level, dual cell memory device. The method includes independently programming a first charge storing cell and a second charge storing cell to respective data states, the data states selected from a blank program level or one of a plurality of charged program levels. Also disclosed is a method of reading the multi-level, dual cell memory device using a plurality of reference currents.Type: GrantFiled: April 15, 2003Date of Patent: October 18, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Darlene G. Hamilton, Kulachet Tanpairoj, Edward Hsia, Yi He
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Patent number: 6944057Abstract: A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.Type: GrantFiled: May 6, 2003Date of Patent: September 13, 2005Assignee: FASL LLCInventors: Edward F. Runnion, Tien-Chun Yang, Binh Quang Le, Shigekazu Yamada, Darlene G. Hamilton, Ming-Huei Shieh, Pau-Ling Chen, Kazuhiro Kurihara
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Patent number: 6901010Abstract: An erase methodology of flash memory cells in a multi-bit memory array with bits disposed in normal and complimentary locations. An erase verify of bits in the normal locations is performed and if a bit in the normal location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the normal bit and the complimentary bit. An erase verify of bits in the complimentary locations is performed and if a bit in the complimentary location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the complimentary and the normal bit locations. If the bits pass the erase verify, the bits are subjected to a soft programming verify. If the bits are overerased and if the soft programming pulse count has not been reached a soft programming pulse is applied to the overerased bit.Type: GrantFiled: April 8, 2002Date of Patent: May 31, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Darlene G. Hamilton, Eric M. Ajimine, Binh Le, Edward Hsia, Ken Tanpairoj
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Patent number: 6897110Abstract: A method of fabricating a memory array, while protecting it from charge damage. Bitlines that may have source/drain regions of memory cells are formed in a substrate. Wordlines are formed above the bitlines and may have gate regions. Next, a first metal region that is coupled to one of the bitlines is formed above the bitlines. A second metal region that is not electrically coupled to the first metal region is formed. Then, the first metal region is electrically coupled to the second metal region. Charge damage is reduced by keeping the antenna ratio between the first metal region and the bitline low. For further protection, a diode or fuse may also be formed between the substrate and the portion of the metal region that is coupled to the bitline. Also, fuse may be formed between a bitline and a wordline to protect the wordline.Type: GrantFiled: November 26, 2002Date of Patent: May 24, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Yi He, Wei Zheng, Zhizheng Liu, Mark W. Randolph, Darlene G. Hamilton, Ken Tanpairoj
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Patent number: 6822909Abstract: A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. The method can include applying an initial program pulse to the memory device; comparing the threshold voltage of the memory device with a verify threshold voltage; and if the threshold voltage of the memory device is less than the verify threshold voltage, applying a second program pulse to the memory device during which at least one condition of the second program pulse is modified from the initial program pulse.Type: GrantFiled: April 24, 2003Date of Patent: November 23, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Darlene G. Hamilton, Edward Hsia, Mark W. Randolph, Edward F. Runnion, Kulachet Tanpairoj
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Patent number: 6813752Abstract: A method of determining charge loss activation for a memory array. Memory arrays are programmed with a pattern for testing charge loss. Then, respective bake times are calculated for the memory arrays to experience a given amount of charge loss at their respective bake temperatures. Then, charge loss activation energy is calculated, based on the respective bake times. In one version, the memory arrays are cycled by repeatedly erasing and reprogramming them before baking. In another embodiment, various regions of the memory arrays are programmed to a plurality of distinct delta threshold voltages before baking.Type: GrantFiled: November 26, 2002Date of Patent: November 2, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Edward Hsia, Darlene G. Hamilton, Wei Zheng, Mark W. Randolph, Kulachet Tanpairoj
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Publication number: 20040208057Abstract: A method of programming a multi-level, dual cell memory device. The method includes independently programming a first charge storing cell and a second charge storing cell to respective data states, the data states selected from a blank program level or one of a plurality of charged program levels. Also disclosed is a method of reading the multi-level, dual cell memory device using a plurality of reference currents.Type: ApplicationFiled: April 15, 2003Publication date: October 21, 2004Inventors: Darlene G. Hamilton, Kulachet Tanpairoj, Edward Hsia, Yi He
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Patent number: 6799256Abstract: A system and methodology is provided for proper reading of multi-bit memory cells in a memory device. A first reference cell and a second reference cell is employed to determine an average dynamic reference value. The average dynamic reference value is determined by reading a programmed bit of the first reference cell and reading an unprogrammed or erased bit of a second reference cell to determine an average dynamic reference value. The average dynamic reference value can be utilized to determine whether data cells are in a programmed state or in an unprogrammed state.Type: GrantFiled: May 1, 2002Date of Patent: September 28, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Michael A. Van Buskirk, Darlene G. Hamilton, Pua-Ling Chen, Kazuhiro Kuribara
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Patent number: 6788583Abstract: A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.Type: GrantFiled: December 2, 2002Date of Patent: September 7, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Yi He, Edward F. Runnion, Zhizheng Liu, Mark W. Randolph, Darlene G. Hamilton, Pauling Chen, Binh Le
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Patent number: 6778442Abstract: A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. According to one aspect of the method, the method can include over-erasing the first and second charge storing cells to shift an erase state threshold voltage of the memory device to be lower than a natural state threshold voltage. According to another aspect of the method, the method can include programming the first and second charge storing cells to the same data state and verifying that the second programmed charge storing cell stores charge corresponding to the data state. If the verification fails, both charge storing cells can be re-pulsed.Type: GrantFiled: April 24, 2003Date of Patent: August 17, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Darlene G. Hamilton, Edward Hsia, Kulachet Tanpairoj, Alykhan Madhani, Mimi Lee