Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

Abstract: A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.

Abstract: A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA level code can specify a routine for storage into the customer code store, at a time prior to its execution. The customer code store thus serves as a write-once execute-many library of pre-decoded routines which ISA level applications can subsequently use, permitting a system manufacturer to create a highly customized and optimized system.

Abstract: A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a replay queue coupled to the checker for temporarily storing one or more instructions for replay. The replay queue may be used to store a long latency instruction, such as a load in which data must be retrieved from an external memory device. The long latency instruction and possibly one or more dependent instruction are stored in the replay queue until the long latency instruction is ready to be executed (e.g., data for the load instruction has been retrieved from external memory). Once the long latency instruction is ready to be executed, (e.g., the data is available), the long latency instruction may then be unloaded from the replay queue for re-execution.

Abstract: In a processing core, a newly received load instruction may be dependent upon a previously received store instruction. The core may include a predictor to predict such dependencies and provide an identification of a colliding store instruction. The load instruction may be stored in a scheduler with a dependency marker. Thereafter, the load instruction may be prevented from executing until after execution of the colliding store. Upon execution of the load, the accuracy of the prediction is confirmed. Upon retirement of the load instruction, new prediction results may be provided to the predictor.

Abstract: A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.

Abstract: The present invention provides a method and apparatus for managing resources in a multithreaded processor. In one embodiment, a resource is partitioned into a number of portions based upon a number of threads being executed concurrently. Resource allocation for each thread is performed in its respective portion of the resource.

Abstract: In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.

Abstract: Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprises a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

Abstract: Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

Abstract: A branch ordering buffer. One disclosed apparatus includes a processor state management circuit to maintain a primary state and a shadow state, each of the primary state and the shadow state including mappings from logical registers to physical registers. The primary state is a speculative state. This disclosed apparatus also includes a branch ordering circuit to prevent the shadow state from advancing beyond a branch instruction until commitment of the branch instruction.

Abstract: A mechanism is provided for allowing a processor to recover from a failure of a predicted path of instructions (e.g., from a mispredicted branch or other event). The mechanism includes a plurality of physical registers, each physical register can store either architectural data or speculative data. The apparatus also includes a primary array to store a mapping from logical registers to physical registers, the primary array storing a speculative state of the processor. The apparatus also includes a buffer coupled to the primary array to store information identifying which physical registers store architectural data and which physical registers store speculative data. According to another embodiment, a history buffer is coupled to the secondary array and stores historical physical register to logical register mappings performed for each of a plurality of instructions part of a predicted path.

Abstract: A control word register, which is specified in a load control word instruction, is renamed and mapped into one of a plurality of physical control word registers. The renaming is performed by a rename logic, which allows for more than one physical control word register to be available for an instruction specifying a given logical control word register.

Abstract: A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.

Abstract: In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.

Abstract: A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.

Abstract: In a processing core, a newly received load instruction may be dependent upon a previously received store instruction. The core may include a predictor to predict such dependencies and provide an identification of a colliding store instruction. The load instruction may be stored in a scheduler with a dependency marker. Thereafter, the load instruction may be prevented from executing until after execution of the colliding store. Upon execution of the load, the accuracy of the prediction is confirmed. Upon retirement of the load instruction, new prediction results may be provided to the predictor.

Abstract: In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.

Abstract: A mechanism is provided for allowing a processor to recover from a failure of a predicted path of instructions (e.g., from a mispredicted branch or other event). The mechanism includes a plurality of physical registers, each physical register can store either architectural data or speculative data. The apparatus also includes a primary array to store a mapping from logical registers to physical registers, the primary array storing a speculative state of the processor. The apparatus also includes a buffer coupled to the primary array to store information identifying which physical registers store architectural data and which physical registers store speculative data. According to another embodiment, a history buffer is coupled to the secondary array and stores historical physical register to logical register mappings performed for each of a plurality of instructions part of a predicted path.

Abstract: A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read request and setting an inuse field associated with the instruction to inuse. Alternate embodiments of the method involve transmitting the instruction in response to the read request, receiving a notification of instruction retirement and resetting the inuse field in the ITLB. The method can also be used in the ICACHE in which inuse fields are associated with each instruction stored in the ICACHE. Other embodiments of the method can be used concurrently in the ITLB and the ICACHE as a resource tracking mechanism to maintain resources.