Abstract: A method includes providing a highly linear front end in a Radio Frequency (RF) receiver, implementing a high Effective Number of Bits (ENOB) Analog to Digital Converter (ADC) circuit in the RF receiver, and sampling, through the high ENOB ADC circuit, at a frequency having harmonics that do not coincide with a desired signal component of an input signal of the RF receiver to eliminate spurs within a data bandwidth of the RF receiver. The input signal includes the desired signal component and an interference signal component. The interference signal component has a higher power level than the desired signal component. The method also includes simultaneously accommodating the desired signal component and the interference signal component in the RF receiver based on an increased dynamic range of the RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.

Abstract: A method includes providing a highly linear front end in a Radio Frequency (RF) receiver, implementing a high Effective Number of Bits (ENOB) Analog to Digital Converter (ADC) circuit in the RF receiver, and sampling, through the high ENOB ADC circuit, at a frequency having harmonics that do not coincide with a desired signal component of an input signal of the RF receiver to eliminate spurs within a data bandwidth of the RF receiver. The input signal includes the desired signal component and an interference signal component. The interference signal component has a higher power level than the desired signal component. The method also includes simultaneously accommodating the desired signal component and the interference signal component in the RF receiver based on an increased dynamic range of the RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.

Abstract: A transconductance comparator includes a comparator having an output of a detector configured to sense an amplitude of an output of a Variable Gain Amplifier (VGA) of a receiver as a first input and a reference amplitude level as a second input. The comparator generates an error signal based on the first input and the second input. The transconductance comparator also includes a transconductance amplifier having a differential voltage input based on the error signal generated through the comparator and generating an output current. The transconductance amplifier includes current sources associated with programmable current limits thereof and differential pairs associated with the current sources, one or more of which is implemented with a size mismatch between transistors thereof to eliminate an offset error due to a mismatch between the current limits, thereby enabling programmability of an attack time and a decay time during automatic gain control of the VGA.

Abstract: A method and Phase Frequency Detector (PFD) circuit for implementing low phase locked loop (PLL) phase noise and low phase error, and a design structure on which the subject circuit resides are provided. The PFD circuit includes a PFD latch receiving clock and reset signals, and PFD output driver circuit providing PFD output signals. The PFD latch is set by the clock and reset by the reset signal. An AND gate coupled to the PFD latch and the PFD output driver circuit includes differential inputs and outputs and applies the reset signal to the PFD latch. The PFD latch, AND gate and PFD output driver circuit are formed by current mode logic using bipolar transistors. An active loop filter generates a tuning voltage output.