Abstract: A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.

Abstract: A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.

Abstract: An N-phase clock generation circuit includes an input clock signal comprising a first phase signal, a phase interpolator configured to receive the input clock signal and generate a second phase signal, a first divider element configured to receive the first phase signal and generate an in-phase divided clock signal, a second divider element configured to receive the second phase signal and generate a quadrature divided clock signal, a first delay element configured to receive the in-phase divided clock signal and an in-phase control signal, the first delay element configured to generate a delayed in-phase divided clock signal, an a second delay element configured to receive the quadrature divided clock signal and a quadrature control signal, the second delay element configured to generate a delayed quadrature divided clock signal.

Abstract: A correlation engine includes a first register configured to receive a test data signal, a second register configured to receive a main data signal, first shift logic configured to shift the test data signal by a predetermined value between 0 and 3 symbols, second shift logic configured to shift the main data signal by a predetermined value between 0 and 20 symbols, and comparison logic configured to compare the shifted test data signal and the shifted main data signal to generate an error signal.

Abstract: A serial-to-parallel converter includes a first register bank having first and second register groups, the first register bank configured to receive a communication signal having at least one bit for each unit interval (UI) of a system clock signal, the first register bank having a number of registers corresponding to a number of parallel processing stages, a second register bank having a plurality of register groups, each register group configured to receive the output of at least one of the first and second register groups after a number of unit intervals corresponding to the number of registers in each of the first and second register groups in the first register bank, and a third register bank configured to receive the output of the second register bank after a number of unit intervals corresponding to a number of registers in the second register bank.

Abstract: A series of logic clouds is used to distribute and propagate signals traveling a relatively long distance across a data logic circuit fabric. One or more long distance signals originate from an initial logic cloud that may be located on a source data block and pass through a series of logic clouds that may be located on an intermediate data block before passing through a destination logic cloud located on a destination data block. Each logic cloud reads both stabilized logic signals and long distance signals and employs a NAND gate connected with an inverter to perform not only logical operations but also to act as a repeater between the logic clouds. The stabilized logic signals may represent signals that originate from other sources along a given data path.

Abstract: A series of logic clouds is used to distribute and propagate signals traveling a relatively long distance across a data logic circuit fabric. One or more long distance signals originate from an initial logic cloud that may be located on a source data block and pass through a series of logic clouds that may be located on an intermediate data block before passing through a destination logic cloud located on a destination data block. Each logic cloud reads both stabilized logic signals and long distance signals and employs a NAND gate connected with an inverter to perform not only logical operations but also to act as a repeater between the logic clouds. The stabilized logic signals may represent signals that originate from other sources along a given data path.

Abstract: An apparatus and method of shifting a low-voltage-swing digital signal to a signal of the same polarity with a relatively higher voltage swing are described which eliminate static current consumption by way of a feedback circuit and a pull-up device. By the use of embodiments according to the invention, little power is consumed, and hot electron injection as a mechanism for FET degradation is of little concern. Additionally, no specialized reference voltage is necessary, and precise layout of the circuit is not critical to proper circuit performance.