Abstract: Processing medical records may be provided. First, medical records may be received from a plurality of sources. The medical records may then be converted into a computer-readable form. Once converted, the medical records may be searched for certain key words, phrases, or symbols. These searched key words, phrases and symbols may correspond to data of interest within the medical records. Once located, the searched key words, phrases and symbols may be extracted from the medical records, as well as an area of the records surrounding the located key words, phrases and symbols. Finally, the extracted data may be used to generate a summary report.

Abstract: Processing medical records may be provided. First, medical records may be received from a plurality of sources. The medical records may then be converted into a computer-readable form. Once converted, the medical records may be searched for certain key words, phrases, or symbols. These searched key words, phrases and symbols may correspond to data of interest within the medical records. Once located, the searched key words, phrases and symbols may be extracted from the medical records, as well as an area of the records surrounding the located key words, phrases and symbols. Finally, the extracted data may be used to generate a summary report.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without comprising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without comprising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without comprising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: A dynamic random access memory (DRAM) cell and associated array are disclosed. In a first embodiment, the DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) is formed within a silicon mesa (310), and includes a source region (316), drain region (318) and channel region (320). The channel region (320) is formed below a furrow (322) that is inset with respect to the top surface of the silicon mesa (310). The channel region (320) has a smaller thickness than that of the source region (316) and drain region (318). A top gate (314) is disposed over the channel region (320). Due to the reduced thickness channel region (320), greater control of the operation of the pass transistor (302) is provided, including an off state with reduced source-to-drain leakage. The greater thickness of the source region (316) and drain region (318) (relative to the channel region (320)) provides greater immunity to the adverse effects of contact spiking.

Abstract: A dynamic random access memory (DRAM) cell and associated array are disclosed. In a first embodiment, the DRAM (300) includes a storage capacitor (308) and a pass transistor (306). The pass transistor (306) is formed within a silicon mesa (314), and includes a source region (320), a drain region (322), and a channel region (324) that extends in a length direction between the source region (320) and drain region (322). When viewed with respect to a width direction, the channel region (324) has a narrower width than that of the source region (320) and drain region (322). Further, the channel region (324) has a top surface and opposing side surfaces. A surrounding gate (318) is disposed around the channel region (324), adjacent to the top and side surfaces, and separated therefrom by a gate insulating layer (316).

Abstract: The described embodiments of the present invention provide a substrate slew circuit that eliminates electron injection. The slew circuit comprises a semiconductor substrate, at least one transistor and a control circuit. One of source/drain of a first transistor (26) in the slew circuit is connected to Vss, the other of the source/drain of the first transistor (26) is connected to the substrate, or in another embodiment of the invention, to one of a source/drain of a second transistor (28), the gate and other of the source/drain of the second transistor (28) being connected to the substrate. A control circuit is connected to the gate of the first transistor for controlling the passage of voltage from the one of a source/drain of the first transistor (26) to the substrate via the gate and the one of a source/drain of the second transistor (28).

Abstract: The described embodiments of the present invention provide a substrate slew circuit that eliminates electron injection. The slew circuit comprises a semiconductor substrate, first and second transistors and a control circuit. One of a source/drain of the source/drain of the first transistor is connected to a reference voltage. One of a source/drain of the second transistor is connected to a gate of the first transistor, the other of the source/drain of the second transistor is coupled to receive a first voltage signal from a substrate pump. The control circuit is connected to the gate of the second transistor for controlling the passage of current from the other of the source/drain of the second transistor to the one of a source/drain of the second transistor.

Abstract: The described embodiments of the present invention provide a substrate slew circuit that eliminates electron injection. The slew circuit comprises a semiconductor substrate, at least one transistor and a control circuit. One of a source/drain of a first transistor in the slew circuit is connected to Vss, the other of the source/drain of the first transistor is connected to the gate and one of a source/drain of a second transistor, the other of the source/drain of the second transistor is connected to the substrate. A control circuit is connected to the gate of the first transistor for controlling the passage of voltage from the one of a source/drain of the first transistor to the substrate via the gate and the one of a source/drain of the second transistor. The sensitivity of the slew circuit can be made programmable by adding one or more more n-channel transistors in stacked diode configuration between the other of the source/drain of the first transistor and the substrate.