Patents by Inventor Daryl L. Habersetzer
Daryl L. Habersetzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6903991Abstract: Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.Type: GrantFiled: June 24, 2002Date of Patent: June 7, 2005Assignee: Micron Technology, Inc.Inventors: Patrick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer
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Patent number: 6882587Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.Type: GrantFiled: June 30, 2004Date of Patent: April 19, 2005Assignee: Micron Technology, Inc.Inventors: Kurt D. Beigel, Manny K. Ma, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer, Jeffrey D. Bruce, Eric T. Stubbs
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Patent number: 6834022Abstract: A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored automatically by the memory device during a memory operation mode or manually by a user during a programming mode.Type: GrantFiled: November 18, 2003Date of Patent: December 21, 2004Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
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Publication number: 20040240286Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.Type: ApplicationFiled: June 30, 2004Publication date: December 2, 2004Inventors: Kurt D. Beigel, Manny K. Ma, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer, Jeffrey D. Bruce, Eric T. Stubbs
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Patent number: 6826071Abstract: A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verifying whether antifuses have been programmed properly in a semiconductor memory.Type: GrantFiled: March 15, 2002Date of Patent: November 30, 2004Assignee: Micron Technology, Inc.Inventors: Patrick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer
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Publication number: 20040223397Abstract: A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verifying whether antifuses have been programmed properly in a semiconductor memory.Type: ApplicationFiled: March 15, 2002Publication date: November 11, 2004Applicant: MICRON TECHNOLOGY, INC.Inventors: Patick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer
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Patent number: 6778452Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.Type: GrantFiled: June 27, 2003Date of Patent: August 17, 2004Assignee: Micron Technology, Inc.Inventors: Kurt D. Beigel, Douglas J. Cutter, Manny K. Ma, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer, Jeffrey D. Bruce, Eric T. Stubbs
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Publication number: 20040100847Abstract: A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or automatically.Type: ApplicationFiled: November 18, 2003Publication date: May 27, 2004Applicant: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
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Publication number: 20040095822Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.Type: ApplicationFiled: June 27, 2003Publication date: May 20, 2004Inventors: Kurt D. Beigel, Douglas J. Cutter, Manny K. Ma, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer, Jeffrey D. Bruce, Eric T. Stubbs
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Patent number: 6661693Abstract: Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.Type: GrantFiled: June 24, 2002Date of Patent: December 9, 2003Assignee: Micron TechnologyInventors: Patrick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer
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Patent number: 6650587Abstract: A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or automatically.Type: GrantFiled: November 19, 2001Date of Patent: November 18, 2003Assignee: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
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Patent number: 6646459Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.Type: GrantFiled: March 19, 2001Date of Patent: November 11, 2003Assignee: Micron Technology, Inc.Inventors: Daryl L. Habersetzer, Casey R. Kurth, Patrick J. Mullarkey, Jason E. Graalum
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Publication number: 20030185080Abstract: A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from a first to a second voltage; detecting whether the voltage at the node charges to the second voltage, or remains at the first voltage to indicate that the antifuse is leaky; outputting signals indicating the result of the detection; and detecting the voltage at the node remains at the first voltage indicates that the antifuse is leaky. In another embodiment, a method of verifying whether antifuses have been programmed properly in a semiconductor memory.Type: ApplicationFiled: March 15, 2002Publication date: October 2, 2003Applicant: MICRON TECHNOLOGY, INC.Inventors: Patick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer
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Patent number: 6600687Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.Type: GrantFiled: September 23, 2002Date of Patent: July 29, 2003Assignee: Micron Technology, Inc.Inventors: Kurt D. Beigel, Manny K. Ma, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer, Jeffrey D. Bruce, Eric T. Stubbs
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Patent number: 6590407Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.Type: GrantFiled: August 16, 2002Date of Patent: July 8, 2003Assignee: Micron Technology, Inc.Inventors: Daryl L. Habersetzer, Casey R. Kurth, Patrick J. Mullarkey, Jason E. Graalum
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Patent number: 6570400Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.Type: GrantFiled: March 29, 2002Date of Patent: May 27, 2003Assignee: Micron Technology, Inc.Inventors: Daryl L. Habersetzer, Casey R. Kurth, Patrick J. Mullarkey, Jason E. Graalum
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Publication number: 20030095459Abstract: A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or automatically.Type: ApplicationFiled: November 19, 2001Publication date: May 22, 2003Applicant: Micron Technology, Inc.Inventors: Scott J. Derner, Casey R. Kurth, Daryl L. Habersetzer
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Publication number: 20030021171Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.Type: ApplicationFiled: September 23, 2002Publication date: January 30, 2003Inventors: Kurt D. Beigel, Manny K. Ma, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer, Jeffrey D. Bruce, Eric T. Stubbs
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Publication number: 20030020508Abstract: A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched, and thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage.Type: ApplicationFiled: August 16, 2002Publication date: January 30, 2003Inventors: Daryl L. Habersetzer, Casey R. Kurth, Patrick J. Mullarkey, Jason E. Graalum
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Publication number: 20020167831Abstract: Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.Type: ApplicationFiled: June 24, 2002Publication date: November 14, 2002Applicant: MICRON TECHNOLOGY, INC.Inventors: Patrick J. Mullarkey, Casey R. Kurth, Jason Graalum, Daryl L. Habersetzer