Patents by Inventor Daryl Sakaida

Daryl Sakaida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9229026
    Abstract: An accelerometer system can include a sensor element comprising first and second proofmasses, the first proofmass accelerating in a first direction and the second proofmass accelerating in a second direction opposite the first direction in response to an external acceleration. A force rebalance controller applies control signals to at least one control element to provide a first force to accelerate the first proofmass toward a first null position and to at least one control element to provide a second force to accelerate the second proofmass toward a second null position. The force rebalance controller can also generate opposite polarity first and second output signals associated with respective displacements of the first and second proofmasses relative to the respective first and second null positions. An acceleration component calculates the external acceleration based on the first and second output signals.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: January 5, 2016
    Assignee: Northrop Grumman Guaidance and Electronics Company, Inc.
    Inventors: Robert E. Stewart, Daryl Sakaida, Michael D. Bulatowicz, Ming Li, John Thomson Douglass
  • Patent number: 8579502
    Abstract: A method for optimizing direct wafer bond line width for reduction of parasitic capacitance in a MEMS device by reducing the width of a bond line between a first and a second wafer, exposing the MEMS device to a water vapor for a predetermined time period and at a first temperature capable of evaporating water, cooling the MEMS device at a second temperature capable of freezing the water, and operating the MEMS device at a third temperature capable of freezing the water to determine if there is discontinuity during operation.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: November 12, 2013
    Assignee: Northrop Grumman Corporation
    Inventors: Henry C. Abbink, Gabriel M. Kuhn, Howard Ge, Daryl Sakaida
  • Publication number: 20120265481
    Abstract: An accelerometer system can include a sensor element comprising first and second proofmasses, the first proofmass accelerating in a first direction and the second proofmass accelerating in a second direction opposite the first direction in response to an external acceleration. A force rebalance controller applies control signals to at least one control element to provide a first force to accelerate the first proofmass toward a first null position and to at least one control element to provide a second force to accelerate the second proofmass toward a second null position. The force rebalance controller can also generate opposite polarity first and second output signals associated with respective displacements of the first and second proofmasses relative to the respective first and second null positions. An acceleration component calculates the external acceleration based on the first and second output signals.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Inventors: ROBERT E. STEWART, Daryl Sakaida, Michael D. Bulatowicz, Ming Li, John Thomson Douglass
  • Publication number: 20110271744
    Abstract: A method for optimizing direct wafer bond line width for reduction of parasitic capacitance in a MEMS device by reducing the width of a bond line between a first and a second wafer, exposing the MEMS device to a water vapor for a predetermined time period and at a first temperature capable of evaporating water, cooling the MEMS device at a second temperature capable of freezing the water, and operating the MEMS device at a third temperature capable of freezing the water to determine if there is discontinuity during operation.
    Type: Application
    Filed: July 19, 2011
    Publication date: November 10, 2011
    Applicant: Northrop Grumman Systems Corporation
    Inventors: Henry C. Abbink, Gabriel M. Kuhn, Howard Ge, Daryl Sakaida
  • Patent number: 8007166
    Abstract: A method for optimizing direct wafer bond line width for reduction of parasitic capacitance in a MEMS device by reducing the width of a bond line between a first and a second wafer, exposing the MEMS device to a water vapor for a predetermined time period and at a first temperature capable of evaporating water, cooling the MEMS device at a second temperature capable of freezing the water, and operating the MEMS device at a third temperature capable of freezing the water to determine if there is discontinuity during operation.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: August 30, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Henry C. Abbink, Gabriel M. Kuhn, Howard Ge, Daryl Sakaida
  • Publication number: 20080184778
    Abstract: A method for optimizing direct wafer bond line width for reduction of parasitic capacitance in a MEMS device by reducing the width of a bond line between a first and a second wafer, exposing the MEMS device to a water vapor for a predetermined time period and at a first temperature capable of evaporating water, cooling the MEMS device at a second temperature capable of freezing the water, and operating the MEMS device at a third temperature capable of freezing the water to determine if there is discontinuity during operation.
    Type: Application
    Filed: May 24, 2006
    Publication date: August 7, 2008
    Applicant: Northrop Grumman Corporation
    Inventors: Henry C. Abbink, Gabriel M. Kuln, Howard Ge, Daryl Sakaida
  • Publication number: 20080000606
    Abstract: An apparatus in one example comprises a die structure that comprises a middle layer, a first outside layer, and a second outside layer. The middle layer comprises a cavity that holds an alkali metal, and one of the first outside layer and the second outside layer comprises a channel that leads to the cavity. The middle layer, the first outside layer, and the second outside layer comprise dies from one or more wafer substrates.
    Type: Application
    Filed: September 11, 2007
    Publication date: January 3, 2008
    Inventors: Henry Abbink, William Debley, Christine Geosling, Daryl Sakaida, Robert Stewart
  • Publication number: 20050236460
    Abstract: An apparatus in one example comprises a die structure that comprises a middle layer, a first outside layer, and a second outside layer. The middle layer comprises a cavity that holds an alkali metal, and one of the first outside layer and the second outside layer comprises a channel that leads to the cavity. The middle layer, the first outside layer, and the second outside layer comprise dies from one or more wafer substrates.
    Type: Application
    Filed: April 26, 2004
    Publication date: October 27, 2005
    Inventors: Henry Abbink, William Debley, Christine Geosling, Daryl Sakaida, Robert Stewart