Abstract: A PLL including an adaptive loop filter. The PLL includes a feedback circuit which provides a feedback signal based on an output signal and a phase detector generating an adjust signal based on a frequency of the feedback signal compared with a reference frequency. A charge pump receives the adjust signal and provides a control voltage. The adaptive loop filter includes a capacitor and an adaptive resistance with a current control input. A VCO has an output providing the output signal based on a voltage level of the control voltage. A bias generator converts the control voltage to a loop bias current, and has a bias output based on the loop bias current coupled to the current control input of the adaptive resistance. The bias output of the bias generator may also be used to control the charge current and the VCO using currents proportional to the loop bias current.

Abstract: A phase locked loop including first and second charge pumps, a voltage buffer and a bias generator for adaptive biasing for improved performance. A voltage controlled oscillator, feedback circuit and phase detector portions may be provided to operate similar to conventional configurations. The first charge pump receives an adjust signal, such as from the phase detector, and selectively charges an intermediate node. The second charge pump receives the adjust signal and selectively charges a control node developing the control voltage for the VCO. A loop filter capacitor is referenced to the intermediate node. The voltage buffer, replacing the loop filter resistor, buffers the intermediate node and drives the control node. The bias generator converts the control voltage to a converter bias current based on the control voltage and adjusts the charge pump currents and a bias current of the voltage buffer.