Patents by Inventor David A. Kewley
David A. Kewley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990367Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.Type: GrantFiled: August 12, 2021Date of Patent: May 21, 2024Inventors: Xiaosong Zhang, Yongjun J. Hu, David A. Kewley, Md Zahid Hossain, Michael J. Irwin, Daniel Billingsley, Suresh Ramarajan, Robert J. Hanson, Biow Hiem Ong, Keen Wah Chow
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Patent number: 11990370Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.Type: GrantFiled: October 21, 2022Date of Patent: May 21, 2024Assignee: Micron Technology, Inc.Inventors: Trupti D. Gawai, David S. Pratt, Ahmed M. Elsied, David A. Kewley, Dale W. Collins, Raju Ahmed, Chelsea M. Jordan, Radhakrishna Kotti
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Patent number: 11978527Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: March 11, 2022Date of Patent: May 7, 2024Assignee: Micron Technology, Inc.Inventors: Raju Ahmed, David A. Kewley, Dave Pratt, Yung-Ta Sung, Frank Speetjens, Gurpreet Lugani
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Integrated Circuitry, Array Of Cross-Point Memory Cells, Method Used In Forming Integrated Circuitry
Publication number: 20230371282Abstract: Integrated circuitry comprises a horizontally-elongated insulative wall directly above a conductive node. The wall comprises insulative material. A conductive via extends through the wall to the conductive node. A conductive line is directly above the wall and directly above the conductive via. The conductive via directly electrically couples together the conductive line with the conductive node. Insulator material is longitudinally-along laterally-opposing sides of the wall. An interface of the insulative material of the wall and the insulator material are on each of the laterally-opposing sides of the wall. Other embodiments, including method, are disclosed.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Applicant: Micron Technology, Inc.Inventors: David A. Kewley, Kevin Baker, Trupti D. Gawai -
Publication number: 20230354595Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.Type: ApplicationFiled: June 12, 2023Publication date: November 2, 2023Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
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Publication number: 20230335439Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures. Memory cells vertically extend through the stack structure, and comprise a channel material vertically extending through the stack structure. An additional stack structure vertically overlies the stack structure and comprises additional conductive structures and additional insulative structures. First pillar structures extend through the additional stack structure and vertically overlie a portion of the memory cells. Second pillar structures are adjacent to the first pillar structures and extend through the additional stack structure and vertically overlie another portion of the memory cells. Slot structures are laterally adjacent to the first pillar structures and to the second pillar structures and extend through at least a portion of the additional stack structure.Type: ApplicationFiled: April 14, 2022Publication date: October 19, 2023Inventors: Chandra S. Tiwari, David A. Kewley, Deep Panjwani, Matthew Holland, Matthew J. King, Michael E. Koltonski, Tom J. John, Xiaosong Zhang, Yi Hu
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Patent number: 11678481Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.Type: GrantFiled: February 11, 2021Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
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Publication number: 20230113573Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.Type: ApplicationFiled: October 21, 2022Publication date: April 13, 2023Inventors: Trupti D. Gawai, David S. Pratt, Ahmed M. Elsied, David A. Kewley, Dale W. Collins, Raju Ahmed, Chelsea M. Jordan, Radhakrishna Kotti
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Publication number: 20230063178Abstract: A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.Type: ApplicationFiled: December 29, 2021Publication date: March 2, 2023Inventors: Bo Zhao, Matthew J. King, Jason Reece, Michael J. Gossman, Shruthi Kumara Vadivel, Martin J. Barclay, Lifang Xu, Joel D. Peterson, Matthew Park, Adam L. Olson, David A. Kewley, Xiaosong Zhang, Justin B. Dorhout, Zhen Feng Yow, Kah Sing Chooi, Tien Minh Quan Tran, Biow Hiem Ong
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Patent number: 11574842Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.Type: GrantFiled: April 14, 2021Date of Patent: February 7, 2023Assignee: Micron Technology, Inc.Inventors: Trupti D. Gawai, David A. Kewley, Aaron M. Lowe, Radhakrishna Kotti, David S. Pratt
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Patent number: 11563027Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.Type: GrantFiled: September 9, 2020Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventors: Md Zakir Ullah, Xiaosong Zhang, Adam L. Olson, Mohammad Moydul Islam, Tien Minh Quan Tran, Chao Zhu, Zhigang Yang, Merri L. Carlson, Hui Chin Chong, David A. Kewley, Kok Siak Tang
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Publication number: 20230021072Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.Type: ApplicationFiled: September 16, 2022Publication date: January 19, 2023Applicant: Micron Technology, Inc.Inventors: Raju Ahmed, Radhakrishna Kotti, David A. Kewley, Dave Pratt
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Patent number: 11515204Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.Type: GrantFiled: December 29, 2020Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Trupti D. Gawai, David S. Pratt, Ahmed M. Elsied, David A. Kewley, Dale W. Collins, Raju Ahmed, Chelsea M. Jordan, Radhakrishna Kotti
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Patent number: 11482492Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.Type: GrantFiled: July 10, 2020Date of Patent: October 25, 2022Assignee: Micron Technology, Inc.Inventors: Raju Ahmed, Radhakrishna Kotti, David A. Kewley, Dave Pratt
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Publication number: 20220336277Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.Type: ApplicationFiled: April 14, 2021Publication date: October 20, 2022Inventors: Trupti D. Gawai, David A. Kewley, Aaron M. Lowe, Radhakrishna Kotti, David S. Pratt
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Publication number: 20220208606Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Inventors: Trupti D. Gawai, David S. Pratt, Ahmed M. Elsied, David A. Kewley, Dale W. Collins, Raju Ahmed, Chelsea M. Jordan, Radhakrishna Kotti
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Publication number: 20220199123Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: March 11, 2022Publication date: June 23, 2022Applicant: Micron Technology, Inc.Inventors: Raju Ahmed, David A. Kewley, Dave Pratt, Yung-Ta Sung, Frank Speetjens, Gurpreet Lugani
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Patent number: 11328749Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: December 18, 2019Date of Patent: May 10, 2022Assignee: Micron Technology, Inc.Inventors: Raju Ahmed, David A. Kewley, Dave Pratt, Yung-Ta Sung, Frank Speetjens, Gurpreet Lugani
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Publication number: 20220077177Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.Type: ApplicationFiled: September 9, 2020Publication date: March 10, 2022Inventors: Md Zakir Ullah, Xiaosong Zhang, Adam L. Olson, Mohammad Moydul Islam, Tien Minh Quan Tran, Chao Zhu, Zhigang Yang, Merri L. Carlson, Hui Chin Chong, David A. Kewley, Kok Siak Tang
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Publication number: 20220013449Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.Type: ApplicationFiled: July 10, 2020Publication date: January 13, 2022Applicant: Micron Technology, Inc.Inventors: Raju Ahmed, Radhakrishna Kotti, David A. Kewley, Dave Pratt