Abstract: A spark-ignited (SI) internal combustion (IC) engine designed to operate on high octane fuels, such as gasoline, is reconfigured to operate on low octane fuels including logistically preferred distillate fuels, such as diesel or JP-8. Design modifications involve coupling a fuel reformer module to the internal combustion engine. Auxiliary components include a system control module, a heat exchange module, a bypass valve to facilitate start-up, and/or a throttle body to control a reformate-oxidizer mixture fed to the engine. Small portable generators having 0.3-3.0 kWe power output are disclosed based upon the modified SI-IC engine design.

Abstract: A system and method for analyzing a device under test is provided. The system includes a signal source for generating an incident signal. The incident signal is routed to one or more inputs of the device under test. The system further includes signal separation and routing circuitry for measuring a portion of the incident signal to provide a reference signal and for separating the incident signal and a reflected signal at the one or more inputs of the device under test. The signal separation circuitry for separating the incident signal and the reflected signal at the input of the device under test is accomplished by a resistive device. The system may further include sampling device operationally coupled to the resistive device. The system and method may further include a signal switching mechanism for sequentially routing time slices of two or more signals to be coherently compared.

Abstract: A system and associated method determines the characteristics of an electric network including distance to a fault through the use of a power divider and a measuring device that measures a quantity from which voltage magnitude can be determined. The measuring device may be a power detector. The power detector may include a power meter to measure voltage and/or a power sensor to measure amplitude. Then, the results from the power detector are used in conjunction with a Hilbert transform to estimate the phase associated with at least two voltage magnitudes when a combined signal is a minimum phase signal.

Abstract: A gas-fired burner adapted for use on a liquid fuel. A method for essentially smokeless start-up and steady state operation of a gas-fired burner on a liquid fuel. The apparatus integrates a catalytic liquid fuel reformer with a flame burner designed for operation on a gaseous fuel of high Wobbe Index, e.g., natural gas. The method involves reacting a mixture of a liquid fuel and oxidant in a catalytic reformer to obtain a gaseous reformate having a low Wobbe Index; and thereafter combusting the gaseous reformate, optionally augmented with liquid co-fuel and oxidant, in the gas-fired burner under diffusion flame conditions. The invention allows commercial gas-fired appliances to be operated on a liquid fuel, thereby offering advantages in logistics and camp operations.

Abstract: A stackable horn configured such that a plurality of substantially identical horns can be stacked to form an array. Each horn diminishes in interior area from a mouth to a throat thereof and is vertically taller and longitudinally deeper than it is wide. The horn or array may be secured to a support. In the array, the horns are similar or identical and are arranged side-by-side with a space in between or in abutting contact. An aperture is defined in the throat of each horn and a microphone is positioned within the throat of each horn in the array. The arrangement of horns in the array permits beamforming and as a result allows simultaneous detection, tracking, and identification of multiple targets. Listening distance is greatly increased by utilizing the horn or the array of horns.

Abstract: A system and method for analyzing a device under test is provided. The system includes a signal source for generating an incident signal. The incident signal is routed to one or more inputs of the device under test. The system further includes signal separation and routing circuitry for measuring a portion of the incident signal to provide a reference signal and for separating the incident signal and a reflected signal at the one or more inputs of the device under test. The signal separation circuitry for separating the incident signal and the reflected signal at the input of the device under test is accomplished by a resistive device. The system may further include sampling device operationally coupled to the resistive device. The system and method may further include a signal switching mechanism for sequentially routing time slices of two or more signals to be coherently compared.

Abstract: A method for synthesizing AEI zeolites is provided which results in high relative yields of AEI based on the weight of the reaction mixture and on the structure directing agent. The method also provides for the reduced use of water in the reaction mixture. A reaction mixture composition comprises the following components: at least one source of silica, at least one source of alumina, at least one structure directing agent (SDA), a source of hydroxide ions and water, where the silica sources and the alumina sources are expressed as SiO2 and Al2O3, respectively, and the components are present in the following ratios: SiO2/Al2O3 ?10-100 OH?/SiO2 0.2-0.9 SDA/SiO2 0.01-0.20 Alkali metal cation/SiO2 0.20-1.0? H2O/SiO2 ??4-60.

Abstract: A spark-ignited (SI) internal combustion (IC) engine designed to operate on high octane fuels, such as gasoline, is reconfigured to operate on low octane fuels including logistically preferred distillate fuels, such as diesel or JP-8. Design modifications involve coupling a fuel reformer module to the internal combustion engine. Auxiliary components include a system control module, a heat exchange module, a bypass valve to facilitate start-up, and/or a throttle body to control a reformate-oxidizer mixture fed to the engine. Small portable generators having 0.3-3.0 kWe power output are disclosed based upon the modified SI-IC engine design.

Abstract: A novel method for synthesizing AEI zeolites is provided which results in high overall relative yields on silica and the structure directing agent.

Abstract: An apparatus and method for operating a gas-fired burner on a liquid fuel. The apparatus integrates a catalytic liquid fuel reformer with a flame burner designed for operation on a gaseous fuel of high Wobbe Index, e.g., natural gas. The method involves reacting a mixture of a liquid fuel and oxidant in a catalytic reformer to obtain a gaseous reformate having a low Wobbe Index; and thereafter combusting the gaseous reformate, optionally augmented with liquid co-fuel and oxidant, in the gas-fired burner under diffusion flame conditions. The invention allows commercial gas-fired appliances, such as stoves, ovens, ranges, grills, griddles, stock pot burners, clothes dryers, hot water heaters, and boilers to be operated on a liquid fuel, which offers advantages in logistics and camp operations.

Abstract: A novel method for synthesizing AEI zeolites is provided which results in high overall relative yields on silica and the structure directing agent. Structure directing agents useful in the present invention include the cations N,N-Dimethyl-3,5-dimethylpiperidinium, N,N-Dimethyl-2-(2-hydroxyethyl)piperidinium, N,N-Dimethyl-2-ethylpiperidinium, and 2,2,4,6,6-Pentamethyl-2-azoniabycyclo[3.2.1]octane.

Abstract: A processor core includes even and odd execution slices each having a register file. The slices are each configured to perform operations specified in a first set of instructions on data from its respective register file, and together configured to perform operations specified in a second set of instructions on data stored across both register files. During utilization, the processor receives a first instruction of the first set specifying an operation, a target register, and a source register. Next, a second instruction upon which content of the source register depends is identified as being of the second set. In response, the first instruction is dispatched to the even slice. In accordance with the operation specified in the first instruction, the even slice uses content of the source register in its register file to produce a result. Copies of the result are written to the target register in both register files.

Abstract: A processor core includes even and odd execution slices each having a register file. The slices are each configured to perform operations specified in a first set of instructions on data from its respective register file, and together configured to perform operations specified in a second set of instructions on data stored across both register files. During utilization, the processor receives a first instruction of the first set specifying an operation, a target register, and a source register. Next, a second instruction upon which content of the source register depends is identified as being of the second set. In response, the first instruction is dispatched to the even slice. In accordance with the operation specified in the first instruction, the even slice uses content of the source register in its register file to produce a result. Copies of the result are written to the target register in both register files.

Abstract: A list of input registers and output registers for a circuit design are provided. The circuit design is modified by traversing output connections paths for each input register and replacing any register in the output connection paths with a wire unless the register is a listed output register. An initial total cycle time value for the modified circuit design is determined. A gate level description for the modified circuit design is obtained by a macro synthesis with the initial total cycle time value. The total cycle time value for the modified circuit design is then varied in order to determine the theoretical limit of the modified circuit design. This theoretical limit is realized when negative slacks are present in a macro synthesis of the modified circuit design for a given total cycle time value. Based on this theoretical limit, the minimum pipeline depth of the circuit design is determined.

Abstract: A novel method for synthesizing AEI zeolites is provided which results in high relative yields of AEI based on the weight of the reaction mixture and on the structure directing agent. The method also provides for the reduced use of water in the reaction mixture.

Abstract: A flight control system for at least one tethered gyroglider along a flight path consistent with at least one flight mission is configured to fly the gyroglider within a portfolio of winds, managing an interaction between portfolios of at least four envelopes including wind, gyroglider performance, flight and base station. Every flight mission corresponds to at least one flight path associated with a set containing at least one first value and at least one second value. The control system is provided with a learning and library manager comprising a repository having stored sets of first values and associated second values for each flight path. The current first values associated with a current mission are corrected based on predicted or experienced flight paths and measurable outputs to attain the desired flight path. The corrected, experienced values, flight path and measurable output are further stored in the repository for further learning.

Abstract: A hardware circuit for returning single precision denormal results to double precision. A hardware circuit component configured to count leading zeros of an unrounded single precision denormal result. A hardware circuit component configured to pre-compute a first exponent and a second exponent for the unrounded single precision denormal result. A hardware circuit component configured to perform a second normalization of the rounded single precision denormal result back to architected format.

Abstract: A processor core includes even and odd execution slices each having a register file. The slices are each configured to perform operations specified in a first set of instructions on data from its respective register file, and together configured to perform operations specified in a second set of instructions on data stored across both register files. During utilization, the processor receives a first instruction of the first set specifying an operation, a target register, and a source register. Next, a second instruction upon which content of the source register depends is identified as being of the second set. In response, the first instruction is dispatched to the even slice. In accordance with the operation specified in the first instruction, the even slice uses content of the source register in its register file to produce a result. Copies of the result are written to the target register in both register files.

Abstract: A processor core includes even and odd execution slices each having a register file. The slices are each configured to perform operations specified in a first set of instructions on data from its respective register file, and together configured to perform operations specified in a second set of instructions on data stored across both register files. During utilization, the processor receives a first instruction of the first set specifying an operation, a target register, and a source register. Next, a second instruction upon which content of the source register depends is identified as being of the second set. In response, the first instruction is dispatched to the even slice. In accordance with the operation specified in the first instruction, the even slice uses content of the source register in its register file to produce a result. Copies of the result are written to the target register in both register files.

Abstract: A hardware circuit for returning single precision denormal results to double precision. A hardware circuit component configured to count leading zeros of an unrounded single precision denormal result. A hardware circuit component configured to pre-compute a first exponent and a second exponent for the unrounded single precision denormal result. A hardware circuit component configured to perform a second normalization of the rounded single precision denormal result back to architected format.