Patents by Inventor David A. Munday
David A. Munday has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966281Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.Type: GrantFiled: April 18, 2022Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Sundar Nadathur, Pratik M. Marolia, Henry M. Mitchel, Joseph J. Grecco, Utkarsh Y. Kakaiya, David A. Munday
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Publication number: 20240012466Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.Type: ApplicationFiled: August 14, 2023Publication date: January 11, 2024Inventors: Shiva Rao, David Munday
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Patent number: 11726545Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.Type: GrantFiled: March 3, 2022Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Shiva Rao, David Munday
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Publication number: 20220245022Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.Type: ApplicationFiled: April 18, 2022Publication date: August 4, 2022Inventors: Sundar Nadathur, Pratik M. Marolia, Henry M. Mitchel, Joseph J. Grecco, Utkarsh Y. Kakaiya, David A. Munday
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Publication number: 20220187899Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.Type: ApplicationFiled: March 3, 2022Publication date: June 16, 2022Inventors: Shiva Rao, David Munday
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Patent number: 11307925Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.Type: GrantFiled: March 29, 2018Date of Patent: April 19, 2022Assignee: Intel CorporationInventors: Sundar Nadathur, Pratik M. Marolia, Henry M. Mitchel, Joseph J. Grecco, Utkarsh Y. Kakaiya, David A. Munday
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Patent number: 11287870Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.Type: GrantFiled: July 6, 2020Date of Patent: March 29, 2022Assignee: Altera CorporationInventors: Shiva Rao, David Munday
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Publication number: 20210084869Abstract: An artificially-created honey-yielding environment is established, including a hive and an associated flora cell, within which first and second plant populations cohabit. Within the cell, honey-producing insects from the hive are permitted to forage. One of the populations has been artificially introduced. The other may be indigenous to the cell. The first plant population serves as a primary source of nectar which yields bioactive honey and the second serves as a source of a nutrient, such as protein, which is not abundantly available from the first species at a nutritionally adequate level for sustaining the metabolism and energy of the foraging honey-producing insects for returning to the hive. The first flora population may be a Leptospermum species. An example of the second is Corymbia maculata.Type: ApplicationFiled: December 9, 2020Publication date: March 25, 2021Inventor: David Munday
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Patent number: 10893665Abstract: An artificially-created honey-yielding environment is established, including a hive and an associated flora cell, within which first and second plant populations cohabit. Within the cell, honey-producing insects from the hive are permitted to forage. One of the populations has been artificially introduced. The other may be indigenous to the cell. The first plant population serves as a primary source of nectar which yields bioactive honey and the second serves as a source of a nutrient, such as protein, which is not abundantly available from the first species at a nutritionally adequate level for sustaining the metabolism and energy of the foraging honey-producing insects for returning to the hive. The first flora population may be a Leptospermum species. An example of the second is Corymbia maculata.Type: GrantFiled: August 14, 2018Date of Patent: January 19, 2021Inventor: David Munday
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Publication number: 20200333872Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.Type: ApplicationFiled: July 6, 2020Publication date: October 22, 2020Applicant: Intel CorporationInventors: Shiva Rao, David Munday
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Publication number: 20200178506Abstract: An artificially-created honey-yielding environment is established, including a hive and an associated flora cell, within which first and second plant populations cohabit. Within the cell, honey-producing insects from the hive are permitted to forage. One of the populations has been artificially introduced. The other may be indigenous to the cell. The first plant population serves as a primary source of nectar which yields bioactive honey and the second serves as a source of a nutrient, such as protein, which is not abundantly available from the first species at a nutritionally adequate level for sustaining the metabolism and energy of the foraging honey-producing insects for returning to the hive. The first flora population may be a Leptospermum species. An example of the second is Corymbia maculata.Type: ApplicationFiled: August 14, 2018Publication date: June 11, 2020Inventor: David Munday
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Publication number: 20190042350Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.Type: ApplicationFiled: March 29, 2018Publication date: February 7, 2019Inventors: Sundar Nadathur, Pratik M. Marolia, Henry M. Mitchel, Joseph J. Grecco, Utkarsh Y. Kakaiya, David A. Munday
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Patent number: 9730282Abstract: A switchable luminance LED light bulb, including embodiments that may be used with any common commercial fitting.Type: GrantFiled: August 5, 2015Date of Patent: August 8, 2017Assignee: The Regents of the University of CaliforniaInventors: David Munday, Ryan Baker, Julian Dahan, Russell Petersen, Craig Sloan
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Patent number: 9235529Abstract: The disclosed embodiments provide a system that uses broadcast-based TLB sharing to reduce address-translation latency in a shared-memory multiprocessor system with two or more nodes that are connected by an optical interconnect. During operation, a first node receives a memory operation that includes a virtual address. Upon determining that one or more TLB levels of the first node will miss for the virtual address, the first node uses the optical interconnect to broadcast a TLB request to one or more additional nodes of the shared-memory multiprocessor in parallel with scheduling a speculative page-table walk for the virtual address. If the first node receives a TLB entry from another node of the shared-memory multiprocessor via the optical interconnect in response to the TLB request, the first node cancels the speculative page-table walk. Otherwise, if no response is received, the first node instead waits for the completion of the page-table walk.Type: GrantFiled: August 2, 2012Date of Patent: January 12, 2016Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Pranay Koka, David A. Munday, Michael O. McCracken, Herbert D. Schwetman, Jr.
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Publication number: 20150382416Abstract: A switchable luminance LED light bulb, including embodiments that may be used with any common commercial fitting.Type: ApplicationFiled: August 5, 2015Publication date: December 31, 2015Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: David Munday, Ryan Baker, Julian Dahan, Russell Petersen, Craig Sloan
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Patent number: 9213649Abstract: The disclosed embodiments provide a system that performs distributed page-table lookups in a shared-memory multiprocessor system with two or more nodes, where each of these nodes includes a directory controller that manages a distinct portion of the system's address space. During operation, a first node receives a request for a page-table entry that is located at a physical address that is managed by the first node. The first node accesses its directory controller to retrieve the page-table entry, and then uses the page-table entry to calculate the physical address for a subsequent page-table entry. The first node determines the home node (e.g., the managing node) for this calculated physical address, and sends a request for the subsequent page-table entry to that home node.Type: GrantFiled: September 24, 2012Date of Patent: December 15, 2015Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Pranay Koka, David A. Munday, Michael O. McCracken, Herbert D. Schwetman, Jr.
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Publication number: 20150301949Abstract: The disclosed embodiments provide a system that uses broadcast-based TLB sharing to reduce address-translation latency in a shared-memory multiprocessor system with two or more nodes that are connected by an optical interconnect. During operation, a first node receives a memory operation that includes a virtual address. Upon determining that one or more TLB levels of the first node will miss for the virtual address, the first node uses the optical interconnect to broadcast a TLB request to one or more additional nodes of the shared-memory multiprocessor in parallel with scheduling a speculative page-table walk for the virtual address. If the first node receives a TLB entry from another node of the shared-memory multiprocessor via the optical interconnect in response to the TLB request, the first node cancels the speculative page-table walk. Otherwise, if no response is received, the first node instead waits for the completion of the page-table walk.Type: ApplicationFiled: August 2, 2012Publication date: October 22, 2015Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Pranay Koka, David A. Munday, Michael O. McCracken, Herbert D. Schwetman, JR.
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Patent number: 9144129Abstract: A switchable luminance LED light bulb, including embodiments that may be used with any common commercial fitting.Type: GrantFiled: December 26, 2012Date of Patent: September 22, 2015Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: David Munday, Ryan Baker, Julian Dahan, Russell Petersen, Craig Sloan
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Patent number: 9081706Abstract: The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For instance, the last-level TLB structures of two or more multiprocessor nodes can be configured to act together as either a distributed shared last-level TLB or a directory-based shared last-level TLB. Such TLB-sharing techniques increase the total amount of useful translations that are cached by the system, thereby reducing the number of page-table walks and improving performance. Furthermore, a coherent shared-memory system with a shared last-level TLB can be further configured to fuse TLB and cache misses such that some of the latency of data coherence operations is overlapped with address translation and data cache access latencies, thereby further improving the performance of memory operations.Type: GrantFiled: May 10, 2012Date of Patent: July 14, 2015Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Pranay Koka, Michael O. McCracken, Herbert D. Schwetman, Jr., David A. Munday
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Patent number: 9009446Abstract: The disclosed embodiments provide a system that uses broadcast-based TLB-sharing techniques to reduce address-translation latency in a shared-memory multiprocessor system with two or more nodes that are connected by an electrical interconnect. During operation, a first node receives a memory operation that includes a virtual address. Upon determining that one or more TLB levels of the first node will miss for the virtual address, the first node uses the electrical interconnect to broadcast a TLB request to one or more additional nodes of the shared-memory multiprocessor in parallel with scheduling a speculative page-table walk for the virtual address. If the first node receives a TLB entry from another node of the shared-memory multiprocessor via the electrical interconnect in response to the TLB request, the first node cancels the speculative page-table walk. Otherwise, if no response is received, the first node instead waits for the completion of the page-table walk.Type: GrantFiled: August 2, 2012Date of Patent: April 14, 2015Assignee: Oracle International CorporationInventors: Pranay Koka, David A. Munday, Michael O. McCracken, Herbert D. Schwetman, Jr.