Patents by Inventor David Allen Brown
David Allen Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Compounding device system, software and method for controlling the process of compounding admixtures
Patent number: 11911736Abstract: An exemplary compounding method of controlling a compounding device to prepare an admixture of at least two distinct material sources can include examining material source solutions for incompatibility of the ingredients and operating a first and a second pump to prevent one of the incompatible source solutions from entering a common flow path. The processing method can detect degradation of a fluid line by evaluating one or more of calibration error rate data, cumulative volumetric flow data, or cumulative pump operation data. The processing method can also selectively transfer a first group of source solutions using the first pump, receiving pump data from one or more sensors that sense actions of the pumps, applying fluid correction factors and calculating discrete pump movements, the pump movements being indicative of an amount of source solution displacement by a pump, and operating the pumps to selectively dispense the source solution amounts according to a preparation order.Type: GrantFiled: December 7, 2019Date of Patent: February 27, 2024Assignee: B. BRAUN MEDICAL INC.Inventors: Michael Y. Brown, Jacob Albro Cowperthwaite, David Earl Hershey, II, Benjamin Richard Lane, Aaron S. Pearl, Mariano Mumpower, Jeffrey Manfred Gunnarsson, James Austin Kendall, Christopher Allen Gray, Stephanne Suzann Flint, Mark David Steenbarger, Alice Maria Weintraut -
Patent number: 11366689Abstract: A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.Type: GrantFiled: May 31, 2019Date of Patent: June 21, 2022Assignee: NXP USA, Inc.Inventors: Michael Rohleder, George Adrian Ciusleanu, David Allen Brown, Marcus Mueller
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Patent number: 11314686Abstract: An integrated circuit is disclosed that includes a central processing unit (CPU), a random access memory (RAM) configured for storing data and CPU executable instructions, a first peripheral circuit for accessing memory that is external to the integrated circuit, a second peripheral circuit, and a communication bus coupled to the CPU, the RAM, the first peripheral circuit and the second peripheral circuit. The second peripheral circuit includes a first preload register configured to receive and store a first preload value, a first register configured to store first information that directly or indirectly identifies a first location where first instructions of a first task can be found in memory that is external to the integrated circuit, and a counter circuit that includes a counter value. The counter circuit can increment or decrement the counter value with time when the counter circuit is started. A first compare circuit is also included and can compare the counter value to the first preload value.Type: GrantFiled: May 15, 2019Date of Patent: April 26, 2022Assignee: NXP USA, Inc.Inventors: Michael Rohleder, George Adrian Ciusleanu, David Allen Brown, Jeffrey Freeman
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Publication number: 20200272594Abstract: An integrated circuit is disclosed that includes a central processing unit (CPU), a random access memory (RAM) configured for storing data and CPU executable instructions, a first peripheral circuit for accessing memory that is external to the integrated circuit, a second peripheral circuit, and a communication bus coupled to the CPU, the RAM, the first peripheral circuit and the second peripheral circuit. The second peripheral circuit includes a first preload register configured to receive and store a first preload value, a first register configured to store first information that directly or indirectly identifies a first location where first instructions of a first task can be found in memory that is external to the integrated circuit, and a counter circuit that includes a counter value. The counter circuit can increment or decrement the counter value with time when the counter circuit is started. A first compare circuit is also included and can compare the counter value to the first preload value.Type: ApplicationFiled: May 15, 2019Publication date: August 27, 2020Inventors: Michael Rohleder, George Adrian Ciusleanu, David Allen Brown, Jeffrey Freeman
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Publication number: 20200272512Abstract: A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.Type: ApplicationFiled: May 31, 2019Publication date: August 27, 2020Inventors: Michael Rohleder, George Adrian Ciusleanu, David Allen Brown, Marcus Mueller
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Patent number: 10719357Abstract: A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.Type: GrantFiled: May 31, 2019Date of Patent: July 21, 2020Assignee: NXP USA, Inc.Inventors: Michael Rohleder, George Adrian Ciusleanu, David Allen Brown, Marcus Mueller
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Patent number: 7729388Abstract: A processor includes at least a portion of a first split transmit and receive media access controller (MAC), the split transmit and receive MAC having a transmit unit and a receive unit physically separated from one another. An interface for directing signals between the transmit unit and the receive unit of the first split transmit and receive MAC is configurable to multiplex the signals with other signals directed between a transmit unit and a receive unit of at least a second split transmit and receive MAC. The interface may comprise a plurality of channels, each having one or more ports associated therewith, wherein a given signal to be directed between transmit and receive units of a given split transmit and receive MAC is assigned to a particular channel and port of the interface.Type: GrantFiled: March 12, 2004Date of Patent: June 1, 2010Assignee: Agere Systems Inc.Inventors: David Allen Brown, Amit Mahendra Shah
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Patent number: 7574482Abstract: An internal memory controller of a network processor or other type of processor controls access of processor clients to memory instances of an internal memory of the processor. The internal memory controller includes a configurable switching element that is connectable between the clients and the memory instances, and is operative to control access of particular ones of the clients to particular ones of the memory instances. Generally, the configurable switching element is configurable to connect any one of at least a subset of the clients to each of at least a subset of the memory instances. In a first selectable configuration of the configurable switching element, a given one of the processor clients is permitted to access a first set of one or more memory instances, and in a second selectable configuration of the configurable switching element, the given processor client is permitted to access a second set of one or more memory instances, with the second set being different than the first set.Type: GrantFiled: October 31, 2003Date of Patent: August 11, 2009Assignee: Agere Systems Inc.Inventors: David Allen Brown, Amit M. Shah
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Patent number: 7277396Abstract: A processor includes controller circuitry operative to control performance monitoring for at least one flow of cells or other protocol data units received by the processor. The controller circuitry includes a classifier and is operative to access memory circuitry associated with the processor. The classifier is configured to perform at least a first pass classification of at least a subset of the protocol data units. The controller circuitry in conjunction with a first pass classification of a protocol data unit of a first type is operative to execute a first script, and in conjunction with a first pass classification of a protocol data unit of a second type is operative to execute a second script different than the first script. A result of execution of at least one of the first and second scripts is stored in the memory circuitry.Type: GrantFiled: October 31, 2003Date of Patent: October 2, 2007Assignee: Agere Systems Inc.Inventors: David Allen Brown, Robert A. Corley, Asif Q. Khan
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Patent number: 7088719Abstract: A processor having a packet processing order maintenance feature includes classification circuitry operative to identify for each of a plurality of packets received in the processor a corresponding packet flow identifier, control circuitry operatively coupled to the classification circuitry, and at least one operational unit operatively coupled to the control circuitry. The control circuitry is operative to direct one or more packets having a given packet flow identifier to the operational unit(s) in a manner that maintains a desired function call sequencing over the one or more packets having the given packet flow identifier for one or more order-dependent processing tasks in the processor.Type: GrantFiled: December 21, 2001Date of Patent: August 8, 2006Assignee: Agere Systems Inc.Inventors: David Allen Brown, Mauricio Calle, Abraham Prasad
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Publication number: 20050094565Abstract: A processor includes controller circuitry operative to control performance monitoring for at least one flow of cells or other protocol data units (PDUs) received by the processor. The controller circuitry includes a classifier and is operative to access memory circuitry associated with the processor. The classifier is configured to perform at least a first pass classification of at least a subset of the PDUs. The controller circuitry in conjunction with a first pass classification of a PDU of a first type is operative to execute a first script, and in conjunction with a first pass classification of a PDU of a second type is operative to execute a second script different than the first script. A result of execution of at least one of the first and second scripts is stored in the memory circuitry. A performance monitoring output is generated, responsive to receipt of the protocol data unit of the second type, based at least in part on the result of execution of at least one of the first and second scripts.Type: ApplicationFiled: October 31, 2003Publication date: May 5, 2005Inventors: David Allen Brown, Robert Corley, Asif Khan
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Publication number: 20030118023Abstract: A processor having a packet processing order maintenance feature includes classification circuitry operative to identify for each of a plurality of packets received in the processor a corresponding packet flow identifier, control circuitry operatively coupled to the classification circuitry, and at least one operational unit operatively coupled to the control circuitry. The control circuitry is operative to direct one or more packets having a given packet flow identifier to the operational unit(s) in a manner that maintains a desired function call sequencing over the one or more packets having the given packet flow identifier for one or more order-dependent processing tasks in the processor.Type: ApplicationFiled: December 21, 2001Publication date: June 26, 2003Inventors: David Allen Brown, Mauricio Calle, Abraham Prasad
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Patent number: 5655609Abstract: A centralizing tool for use in drilling an earth borehole. Drilling fluid pressure extends contact members radially from the tool into engagement with the borehole walls. A timing wheel engages each of the contact members to coordinate their radial movement. A fluid driven tubular central piston extending through the timing wheel causes the wheel to rotate as the piston is moved axially through the tool. High fluid pressure drives the contact members radially outwardly and moves the piston axially to compress a central coil spring surrounding the piston. Reduction of the drilling fluid pressure allows the spring force to return the piston to its initial axial position which rotates the timing wheel to retract the contact elements.Type: GrantFiled: January 16, 1996Date of Patent: August 12, 1997Assignee: Baroid Technology, Inc.Inventors: David Allen Brown, Lee M. Smith