Patents by Inventor David Alston Lide
David Alston Lide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966777Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.Type: GrantFiled: February 7, 2022Date of Patent: April 23, 2024Assignee: Texas Instruments IncorporatedInventors: Thomas Anton Leyrer, William Cronin Wallace, David Alston Lide
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Patent number: 11704154Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.Type: GrantFiled: June 28, 2021Date of Patent: July 18, 2023Assignee: Texas Instruments IncorporatedInventors: Thomas Anton Leyrer, William Cronin Wallace, Pratheesh Gangadhar Thalakkal Kottilaveedu, David Alston Lide
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Patent number: 11579877Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.Type: GrantFiled: April 6, 2021Date of Patent: February 14, 2023Assignee: Texas Instruments IncorporatedInventors: Thomas Anton Leyrer, William Cronin Wallace, David Alston Lide, Pratheesh Gangadhar Thalakkal Kottilaveedu
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Publication number: 20220164226Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.Type: ApplicationFiled: February 7, 2022Publication date: May 26, 2022Inventors: Thomas Anton LEYRER, William Cronin WALLACE, David Alston LIDE
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Patent number: 11243809Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.Type: GrantFiled: December 18, 2020Date of Patent: February 8, 2022Assignee: Texas Instmments IncorporatedInventors: Thomas Anton Leyrer, William Cronin Wallace, David Alston Lide
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Publication number: 20210326178Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.Type: ApplicationFiled: June 28, 2021Publication date: October 21, 2021Inventors: Thomas Anton LEYRER, William Cronin WALLACE, Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU, David Alston LIDE
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Publication number: 20210224070Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.Type: ApplicationFiled: April 6, 2021Publication date: July 22, 2021Inventors: Thomas Anton LEYRER, William Cronin WALLACE, David Alston LIDE, Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU
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Patent number: 11048552Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.Type: GrantFiled: May 29, 2019Date of Patent: June 29, 2021Assignee: Texas Instruments IncorporatedInventors: Thomas Anton Leyrer, William Cronin Wallace, Pratheesh Gangadhar Thalakkal Kottilaveedu, David Alston Lide
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Publication number: 20210103469Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.Type: ApplicationFiled: December 18, 2020Publication date: April 8, 2021Inventors: Thomas Anton LEYRER, William Cronin WALLACE, David Alston LIDE
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Patent number: 10970074Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.Type: GrantFiled: May 29, 2019Date of Patent: April 6, 2021Assignee: Texas Instruments IncorporatedInventors: Thomas Anton Leyrer, William Cronin Wallace, David Alston Lide, Pratheesh Gangadhar Thalakkal K{dot over (o)}ttilaveedu
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Patent number: 10871992Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.Type: GrantFiled: May 29, 2019Date of Patent: December 22, 2020Assignee: Texas Instruments IncorporatedInventors: Thomas Anton Leyrer, William Cronin Wallace, David Alston Lide
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Publication number: 20190370207Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.Type: ApplicationFiled: May 29, 2019Publication date: December 5, 2019Inventors: Thomas Anton LEYRER, William Cronin WALLACE, Pratheesh Gangadhar THALAKKAL KOTTILAVEEDU, David Alston LIDE
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Publication number: 20190369996Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.Type: ApplicationFiled: May 29, 2019Publication date: December 5, 2019Inventors: Thomas Anton LEYRER, William Cronin WALLACE, David Alston LIDE, Pratheesh Gangadhar Thalakkal Kottilaveedu
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Publication number: 20190370110Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.Type: ApplicationFiled: May 29, 2019Publication date: December 5, 2019Inventors: Thomas Anton LEYRER, William Cronin WALLACE, David Alston LIDE
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Publication number: 20090163254Abstract: A method, system and apparatus for synchronizing multiple streams of a communication session between a wireless station device (STA) and one or more communication devices via a wireless access point (AP) of a wireless local area network (WLAN), includes a host processor determining a synchronization period in accordance with packetization periods of each of the multiple streams, switching the STA to a doze mode until expiration of the synchronization period, buffering packets generated during the synchronization period, and switching the STA from the doze mode to an active mode upon expiration of the synchronization period and decompressing or transmitting packets generated while the STA is in the active mode.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Praphul Chandra, David Alston Lide
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Publication number: 20080025300Abstract: A subscriber device capable of Voice over Internet Protocol (VoIP) communication via a wireless connection with an 802.11 access point to an Internet Protocol (IP) based network includes a codec for encoding a signal into a Real Time Protocol (RTP) packet and a controller for controlling a bit-rate at which the codec encodes the signal. The codec encodes the signal at a first bit-rate during normal transmissions and encodes the signal at a second bit-rate lower than the first bit-rate upon occurrence of a predetermined triggering event.Type: ApplicationFiled: July 31, 2006Publication date: January 31, 2008Applicant: Texas Instruments IncorporatedInventors: David Alston Lide, Praphul Chandra, Samant Kumar