Abstract: A method for encrypting data is provided. The method includes formatting data represented in a weighted number system into data blocks. The method also includes converting the data blocks into a residue number system representation. The method further includes generating a first error generating sequence and inducing errors int he data blocks after converting the data blocks into a residue number system representation. It should be understood that the errors are induced in the data blocks by using the first error generating sequence. After inducing errors into the data blocks, the data of the data blocks is formatted into a form to be sorted or transmitted. The method also includes generating a second error generating sequence synchronized with and identical to the first error generating sequence and correcting the errors in the data blocks using an operation which is an arithmetic of a process used in inducing errors.

Abstract: A system for communicating includes a transmitter that has an encoder and baseband modulator that encodes and modulates a sequence of data symbols as a payload data constellation to be communicated. A PN sequence generator and baseband modulator form a pilot signal as a training sequence with a periodically repeating spread spectrum sequence. A circuit superimposes the pilot signal over the sequence of data symbols to form a composite communication signal that is transmitted. A receiver receives the composite communication signal and extracts the pilot signal from the composite communication signal.

Abstract: A system, method and apparatus includes a transmitter that has an encoder and baseband modulator that encodes and modulates a sequence of payload data symbols as a signal constellation to be communicated. An amble generator and baseband modulator generates amble symbols as a known sequence of M symbol times in length every N symbol times. A multiplexer multiplexes the data and amble symbols together to form a communications signal that is transmitted over a communications channel.

Abstract: A method is provided for generating a chaotic sequence. The method includes selecting a plurality of polynomial equations. The method also includes using residue number system (RNS) arithmetic operations to respectively determine solutions for the polynomial equations. The solutions are iteratively computed and expressed as RNS residue values. The method further includes determining a series of digits in a weighted number system (e.g., a binary number system) based on the RNS residue values. According to an aspect of the invention, the method includes using a Chinese Remainder Theorem process to determine a series of digits in the weighted number system based on the RNS residue values. According to another aspect of the invention, the determining step comprises identifying a number in the weighted number system that is defined by the RNS residue values.

Abstract: A semiconductor device includes a plurality of processing clusters that operate synchronously internally and arranged in a M×N matrix. Each processing cluster is formed as a plurality of processing elements and clocked buses that interconnect the processing elements within each processing cluster. A self-synchronous cluster wrapper is operative with the processing elements such that each processing cluster forms a programmable module. Self-synchronous global and local buses interconnect the processing clusters for communicating externally. An input/output circuit interconnects the global and local buses.

Abstract: A method is provided for tamper detection of a transmitted signal. The method is comprised of generating a first digital data signal having a first data rate. The method is also comprised of generating a second digital data signal having a second data rate. The method is further comprised of concurrently transmitting the first digital data signal at a first carrier frequency using a first modulation format and the second digital data signal at a second carrier frequency using a second modulation format. The method includes selecting the second carrier frequency and a bandwidth of the second digital data signal so that the second digital data signal is contained within a frequency spectrum defined by a bandwidth of the first digital data signal. The method also includes verifying an integrity of the first digital data signal at a remote receiver based on defection at the remote receiver of the second digital data signal. A system (100) is also provided for generating a tamper-protected transmitted signal.

Abstract: An automated inspection system and method enables rapid, remote and non-contact inspection of large objects, utilizing non-destructive inspection techniques, that does not require continuous manual repositioning of the inspection equipment. The inspection system includes a remote controlled robotic vehicle including a sensor package capable of non-destructive inspection of a structure and a mechanism for locating the sensor package at a plurality of inspection sights on the structure; a positioning system for determining the location of the robotic vehicle with respect to the structure to be inspected; a control system for controlling the movement of the robotic vehicle around the structure to be inspected; and an analysis systems for analyzing data generated by the sensor platform.

Abstract: An automated inspection system and method enables rapid, remote and non-contact inspection of large objects, utilizing non-destructive testing techniques, that does not require continuous manual repositioning of the test equipment. The inspection system includes a remote controlled robotic vehicle including a sensor package capable of non-destructive testing of a structure and a mechanism for locating the sensor package at a plurality of test sights on the structure; a positioning system for determining the location of the robotic vehicle with respect to the structure to be tested; a control system for controlling the movement of the robotic vehicle around the structure to be tested; and an analysis systems for analyzing data generated by the sensor platform.

Abstract: A class D amplifier includes a separating circuit for separating a pulse code modulation (PCM) signal into a K least significant bits (LSBs) signal and an L most significant bits (MSBs) signal; a PCM to pulse width modulation (PWM) converter for converting the L MSBs signal into a PWM signal; and an LSB processor for proportionally altering the PWM signal from the PCM to PWM converter based upon the K LSBs signal to define a PWM output control signal. More particularly, the PCM input signal may be an N-1 bit PCM magnitude signal. The amplifier preferably further includes a sign and magnitude extraction circuit for extracting a sign bit signal and the N-1 bit magnitude signal from an N bit two's complement PCM input signal. Accordingly, the class D amplifier may also include a switch driver responsive to the extracted sign bit signal and the PWM output control signal, such as to control polarity and on time, respectively.

Abstract: A class D amplifier includes a scaled clock generator for generating a scaled clock signal based upon an N bit pulse code modulation (PCM) signal and a K most significant bits (MSBs) PCM signal from the N bit PCM signal; and a PCM to pulse width modulation (PWM) converter for converting the K MSBs signal to a PWM output signal based upon the scaled clock signal. The amplifier preferably includes an input circuit for generating the N bit PCM signal from an input signal, and a truncation circuit for truncating the N bit PCM digital signal to the K MSBs PCM signal. The PWM output signal may be coupled to a switch driver which, in turn, is coupled to one or more output switches. The amplifier uses a practically implemented reference clock without the drawbacks associated with a conventional noise shaping filter.

Abstract: An up-converter for digitally sampled baseband signals takes advantage of the sinc(x) spectral replication functionality of a DAC, using a post-DAC, band pass filter to isolate a baseband replica that falls within that sidelobe of the DAC's sinc(x) frequency response containing the desired IF. The parameters of a pre-compensation filter and the gain of a post DAC amplifier are set to compensate for the distortion and attenuation imparted by the DAC's sinc(x) frequency response.

Abstract: A digital down converter with a programmable mixing down frequency and a programmable extraction bandwidth uses a ROM based sin/cos generator plus a programmable high decimation filter followed by a gain compensating scaling multiplier and a fixed FIR filter. Output format options are also programmable, and programming commands are serially loaded into registers. Various components may be isolated for efficient testing and also subsystem operation.

Abstract: A digital down converter with a programmable mixing down frequency and a programmable extraction bandwidth uses a ROM based sin/cos generator plus a programmable high decimation filter followed by a gain compensating scaling multiplier and a fixed FIR filter. Output format options are also programmable, and programming commands are serially loaded into registers. Various components may be isolated for efficient testing and also subsystem operation.

Abstract: A system and method for converting and combining multiple digital baseband signals into a composite IF signal for subsequent up converting and transmitting as an RF signal. The system and method use distributed symmetrical circuit architecture to form a composite IF signal from multiple identical converting elements which are daisy chained together to produce the composite signal from the converted signals in each element. Circuit complexity is reduced by the use of the multiple identical elements each of which may be readily formed from a standard integrated circuit.

Abstract: A quadrature decimation filter with real output formed from a mixture of both in-phase and quadrature signals by upconversion and alternating stream combination. The in-phase and quadrature branch computations run simultaneously with a delay of the in-phase data stream relative to the quadrature data stream so that a common filter coefficient may be used simultaneously in nonzero branch computations.

Abstract: A digital down converter for extracting a signal from a complex digital signal wherein the real and imaginary components of the complex digital signal are each modulated to shift the center frequency of the desired signal to zero frequency, decimated digitally to limit the bandwidth of each to the bandwidth of the desired signal and filtered to alter the shape thereof. The digital down converter includes a formatter for arranging the output of the desired signal in one of multiple output formats and a controller for programmably controlling the modulation, decimation and filtering and for selecting the desired output format.

Abstract: Programmable decimation filter made of integrators and combs with a shortened first integrator register and with a single subtractor plus memory for the combs subtractions. The comb subtractions are serially performed with read/write accesses to the memory. A shifter between the first and second integrator registers provides application to low decimation rates and the shortened register relates to device error rate at high decimation rates.

Abstract: A noncanonic fully systolic least mean squares adaptive filter architecture encompasses both tap weight updates and filtering and allows cascadability without penalties in speed or accuracy. A systolic tap weight update section is followed by a systolic FIR filter section. An array control and alignment section and a forward loading shift register provides a modified coefficient update circuit which facilitates the interface between the two sections. This architecture allows for efficient microprocessor control of the filter algorithm.

Abstract: A sine/cosine generator with coarse and fine angles having compressed sine and cosine read only memories (ROMS) by use of symmetry of coarse angles about .pi./4 and, optionally, symmetry of fine angles about 0. The output of the ROMs directly feed multiplexers for utilization of the compressed storage. Addressing of complementary coarse angles is with one's complementing of the address and of complementary fine angles is with two's commplementing of the address. Fine sines and cosines are stored in recoded version for direct use in multipliers for computations using the sum of angles formulas.

Abstract: A sine/cosine generator with coarse and fine angles having compressed sine and cosine read only memories (ROMS) by use of symmetry of coarse angles about .pi./4 and, optionally, symmetry of fine angles about 0. The output of the ROMs directly feed multiplexers for utilization of the compressed storage. Addressing of complementary coarse angles is with one's complementing of the address and of complementary fine angles is with two's commplementing of the address. Fine sines and cosines are stored in recoded version for direct use in multipliers for computations using the sum of angles formulas.