Abstract: An electrical interconnect structure comprising a diffusion barrier and a method of forming the structure over a semiconductor substrate. A bi-layer diffusion barrier is formed over the substrate. The barrier comprises a capturing layer beneath a blocking layer. The blocking layer is both thicker than the capturing layer and is unreactive with the capturing layer. A conductive layer, thicker than the blocking layer, is then formed over the barrier. While the conductive layer is unreactive with the blocking layer of the barrier, the conductive layer is reactive with the capturing layer of the barrier.

Abstract: An interconnect system is provided. The interconnect system includes a silicon substrate and a first dielectric layer formed upon the silicon substrate. The interconnect system also includes a first level of at least two electrically conductive lines formed upon the first dielectric layer. The interconnect system further includes a region of low dielectric constant material formed between the at least two electrically conductive lines. The interconnect system also includes a first hard mask formed upon the polymer region.

Abstract: A high density, low capacitance, interconnect structure for microelectronic devices has unlanded vias formed with organic polymer intralayer dielectric material having substantially vertical sidewalls. A method of producing unlanded vias includes forming a planarized organic polymer intra-layer dielectric between conductors, forming an inorganic dielectric over the conductor and organic polymer layer, patterning a photoresist layer such that openings in the photoresist layer overlap portions of both the conductor and the intra-layer dielectric, etching the inorganic dielectric and then concurrently stripping the photoresist and anisotropically etching the organic polymer intra-layer dielectric. A second conductor is typically deposited into the via opening so as to form an electrical connection to the first conductor. A silicon based insulator containing an organic polymer can alternatively be used to form the intra-layer dielectric.

Abstract: A method of forming a polycide thin film. First, a silicon layer is formed. Next, a thin barrier layer is formed on the first silicon layer. A second silicon layer is then formed on the barrier layer. Next, a metal layer is formed on the second silicon layer. The metal layer and the second silicon layer are then reacted together to form a silicide.

Abstract: A method of forming a field effect transistor structure for making semiconductor integrated circuits is disclosed. The method utilizes a novel processing sequence where the high temperature processing steps are carried out prior to the formation of the gate dielectric and gate electrode. The process sequence proceeds as follows: A mask patterned in replication of a to-be-formed gate is deposited onto a substrate. Then, a high temperature step of forming doped regions is performed. Then, a high temperature step of forming a silicide is performed. Next, a planarization material is deposited over the mask and is planarized. The mask is removed selectively to the planarization material to form an opening within the planarization material. The gate dielectric and gate electrode are formed within the opening.

Abstract: A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filled with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed.

Abstract: A method of forming a polycide thin film. First, a silicon layer is formed. Next, a thin barrier layer is formed on the first silicon layer. A second silicon layer is then formed on the barrier layer. Next, a metal layer is formed on the second silicon layer. The metal layer and the second silicon layer are then reacted together to form a silicide.

Abstract: A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.

Abstract: A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filed with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed. The second opening is filled with conductive material.

Abstract: An electrical interconnect structure comprising a diffusion barrier and a method of forming the structure over a semiconductor substrate. A bi-layer diffusion barrier is formed over the substrate. The barrier comprises a capturing layer beneath a blocking layer. The blocking layer is both thicker than the capturing layer and is unreactive with the capturing layer. A conductive layer, thicker than the blocking layer, is then formed over the barrier. While the conductive layer is unreactive with the blocking layer of the barrier, the conductive layer is reactive with the capturing layer of the barrier.

Abstract: A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.

Abstract: A device and methods of forming an interconnection within a prepatterned channel in a semiconductor device are described. The present invention includes a method of forming an interconnect channel within a semiconductor device. A first dielectric layer is deposited over a substrate and patterned to form a contact opening that is subsequently filled with a contact plug. A second dielectric layer is deposited over the patterned first dielectric layer and the contact plug. The second dielectric layer is patterned to form the interconnect channel, wherein the first dielectric layer acts as an etch stop to prevent etching of the substrate. The present invention also includes a method of forming an interconnect. A dielectric layer is deposited over a substrate and patterned to form an interconnect chapel. A metal layer is deposited over the patterned dielectric layer and within the interconnect channel.

Abstract: A process for the formation of a planar epitaxial cobalt silicide and for the formation of shallow conformal junctions for use in semiconductor processing. A cobalt silicide and titanium nitride bilayer is formed. The titanium nitride layer is chemically removed. Ions with or without a dopant are then implanted into the cobalt silicide layer. During the ion implantation, at least a portion of the cobalt silicide layer is transformed into an amorphous cobalt silicon mixture while the non-amorphous portion remains single crystal. If the ion implantation contains dopants, then after the implantation is completed, both the amorphous and non-amorphous portions of the cobalt silicide layer contain the dopants. The substrate is then annealed in either an ambient comprising a nitrogen gas or in an oxidizing ambient. During the anneal, the amorphous portion of the silicon substrate recrystallizes into a single crystal cobalt silicide layer.

Abstract: The present invention discloses a method for anisotropically etching metal interconnects in the fabrication of semiconductor devices, especially ULSI interconnects having high aspect ratios. A metal film is first deposited on the appropriate layer of a semiconductor substrate by techniques well-known in the art. A mask layer is deposited over the metal film with openings defined in the mask layer for patterning of the metal film. Ions are then introduced into an exposed region of the metal film to anisotropically form a converted layer of the metal film comprising compounds of the metal. The introduction of the ions into the metal film can be performed by conventional methods, such as through the use of a reactive ion etch system or an ion implantation system, or by any other method which anisotropically forms the metal compounds. The mask layer is then removed by conventional means to leave behind the metal film having a converted layer of metal compounds.

Abstract: A process for the formation of a titanium nitride/cobalt silicide bilayer for use in semiconductor processing. Titanium and then cobalt are deposited on a silicon substrate by sputter deposition techniques. The substrate is then annealed. During this process the titanium first cleans the silicon surface of the substrate of any native oxide. During the anneal, the titanium diffuses upward and the cobalt diffuses downward. The cobalt forms a high quality epitaxial cobalt silicide layer on the silicon substrate. The titanium layer diffuses upward to the surface of the bilayer. The anneal is carried out in a nitrogen or ammonia ambient, so that a titaniun nitride layer is formed.

Abstract: A process which provides for self-aligned contact hole filling leading to complete planarization and low contact resistance at the same time, without the use of additional lithographic masking procedures is described. Further, the resultant conductive plug eliminates spiking problems between aluminum and silicon during a subsequent alloying process. In an embodiment, a selective polysilicon layer is deposited and appropriately doped; a second undoped selective silicon layer is then deposited, followed by a refractory metal layer, These layers are heated to produce a self-aligned refractory metal silicide plug.

Abstract: An image stabilized optical device including an objective lens, an eyepiece lens and a prism-composed, image erection system. The image erection system is disposed in the major optical axis of the device, and is gimballed for rotation about two axes normal to the major optical axis of the device.

Abstract: In a fabrication sequence for VLSI MOS devices, an advantageous alignment mark for a wafer to be directly processed by electron beam lithography is made of tantalum disilicide protected by a silicon nitride layer.

Abstract: A method for simultaneously patterning-over field oxide, gate oxide, and sidewall oxide--high conductivity metal-silicide electrode metallization for semiconductor integrated circuits involves (1) formation of an unpatterned polycrystalline silicon (polysilicon) layer everywhere on the exposed surface of all the oxides, (2) formation of a patterned photoresist layer on the polysilicon layer, (3) deposition of a layer of the metal-silicide over all exposed surfaces, (4) removal of the patterned photoresist layer to lift off metal-silicide, and (5) oxidation of only exposed portions of the polysilicon layer to form silicon dioxide. The polysilicon layer can be originally doped, so that the doped silicon dioxide can then be removed (without removing undoped silicon dioxide) by means of an etchant which attacks the dopant.

Abstract: It is known to deposit a refractory metal silicide on a polysilicon gate layer to form a low-resistivity composite structure. For VLSI MOS devices, very-high-resolution patterning of the composite structure is required. In accordance with this invention, a silicide pattern is formed on polysilicon by a lift-off technique. In turn, the patterned silicide is utilized as a mask for anisotropic etching of the underlying polysilicon. High-conductivity composite silicide-on-polysilicon gate structures for VLSI MOS devices are thereby achieved.