Abstract: Aspects of the disclosure pertain to a system and method for promoting improved error detection efficiency in a Content-Addressable Memory (CAM). The system and method provide CAM continuous error detection with interleave parity. The system continuously monitors for changes in cell contents and, when (e.g., as soon as) a soft error occurs, the error detection output bit for that entry will change, causing an error flag at chip level. The system can then immediately stop compare operations and rewrite the failing entry. Separate read operations are not needed to check for errors, thereby decreasing overall dynamic power usage and increasing possible search frequency for the system.

Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to (i) parse a first data word into a first data portion and a second data portion and (ii) parse a first address into a first address portion and a second address portion. The second circuit generally has a plurality of memory blocks. The second circuit may be configured to store the second data portion in a particular one of the memory blocks using (i) the first data portion to determine the particular memory block and (ii) the first address portion to determine a particular one of a plurality of locations within the particular memory block. The data portion may not be stored in the memory blocks. The particular location may be determined independently of the second address portion.

Abstract: Aspects of the disclosure pertain to a system and method for promoting improved error detection efficiency in a Content-Addressable Memory (CAM). The system and method provide CAM continuous error detection with interleave parity. The system continuously monitors for changes in cell contents and, when (e.g., as soon as) a soft error occurs, the error detection output bit for that entry will change, causing an error flag at chip level. The system can then immediately stop compare operations and rewrite the failing entry. Separate read operations are not needed to check for errors, thereby decreasing overall dynamic power usage and increasing possible search frequency for the system.

Abstract: An apparatus and a method of operating the apparatus. The apparatus includes a driver circuit and a memory circuit. The driver circuit may be configured to precharge a hitline in response to a predetermined voltage level and a control signal and sense a result of a compare operation based upon a hitline signal on the hitline. The driver circuit generally precharges the hitline to a voltage level lower than the predetermined voltage level and senses the result of the compare operation using the full predetermined voltage level. The memory circuit may be configured to perform the compare operation using the hitline.

Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to (i) parse a first data word into a first data portion and a second data portion and (ii) parse a first address into a first address portion and a second address portion. The second circuit generally has a plurality of memory blocks. The second circuit may be configured to store the second data portion in a particular one of the memory blocks using (i) the first data portion to determine the particular memory block and (ii) the first address portion to determine a particular one of a plurality of locations within the particular memory block. The data portion may not be stored in the memory blocks. The particular location may be determined independently of the second address portion.

Abstract: An apparatus comprising a first circuit, a driver circuit and a memory circuit. The first circuit may be configured to generate a supply voltage that changes between (i) a first voltage when an input signal is in a first state and (ii) a second voltage when the input signal is in a second state. The driver circuit may be configured to generate a wordline signal in response to (i) the supply voltage, (ii) a clock signal and (iii) a select signal. The memory circuit may be configured to perform a read/write operation in a response to the wordline signal.

Abstract: A scannable dynamic logic element includes a clock input, a test enable input, a data output, a precharge circuit, a boolean pull-down circuit and a test scan pull-down circuit. The precharge circuit is coupled between a first supply terminal and the data output and has a precharge control input coupled to the clock input. The boolean pull-down circuit is coupled between the data output and the second supply terminal and has a logic data input, a first evaluation control input which is coupled to the clock input and a first enable input which is coupled to the test enable input. The test scan pull-down circuit is coupled between the data output and the second supply terminal and has a test data input, a second evaluation control input which is coupled to the clock input and a second enable input which is coupled to the test enable input.

Abstract: A memory system having a read/write head is provided wherein a system clock or a test clock can be used to initiate a pulse for enabling the read/write head during a write period and a delay circuit coupled to the system clock or to the test clock can be used to terminate the enabling or control pulse, with a write clock having an input coupled to the system clock also used to terminate the enabling or control pulse during a write period.

Abstract: A memory system is provided wherein array signals begin at the start of a first phase of a system clock and a sense amplifier set signal is developed during a second phase of the system clock which includes an array of memory cells including word lines and bit lines, word drivers connected to the word lines, a word address decoder enabled by the first phase of the clock system and coupled to the word drivers, a bit switch coupling a bit line to a sense amplifier, a system clock inverting circuit, a timing circuit having a first input connected to a late select signal, a second input connected to the inverting circuit and an output connected to the bit switch and a delay circuit having an input coupled to the inverting circuit and an output connected to the sense amplifier.