Abstract: A voltage controlled oscillator (VCO) for use in a personal area network synthesizer includes a delay cell (100), a first current amplifier (201, 203) for amplifying an input current, a resister capacitor (RC) tuning network (207, 209, 211) for varying the amount of amplification and delay of an output of the first current amplifier. A second current amplifier (213, 215) is then used for amplifying an output current from the RC tuning network. The invention includes a unique composite voltage variable capacitor (CVVC) (300) for precisely tuning the amount of delay presented by the delay cell. The unique topology of the delay cell (100) allows it to be readily used in voltage controlled oscillators (VCOs) operable at frequencies above 1 GHz.

Abstract: A system for coarsely tuning at least one voltage controlled oscillator (VCO) (211) in a phase locked loop (PLL) synthesizer (200) that includes a phase-frequency detector (PFD) for determining a phase difference between a VCO frequency and a reference frequency and providing an error signal if the VCO frequency and reference frequency are at least 2&pgr; radians out of phase. A monitor (215) is then used for tracking the number of error signals produced by the PFD. The free running frequency of the VCO may be coarsely tuned in the event the monitor circuit reaches some predetermined level. The invention offers great advantage in enabling a PLL to be coarsely tuned to enable the PLL's VCO to remain with an operational range despite operational factors that effect circuit operation.

Abstract: A differential amplitude detection circuit (10) passes the positive and negative components of a data communication differential signal through peak detector circuits (12) and (26), respectively. The peak detected voltages are held at first (15) and second (37) nodes by holding capacitors (14) and (28). Current loads (18) and (30) sink predetermined currents from the first and second nodes to prevent the peak voltages from becoming accumulated by the holding capacitors. The peak detected voltages are summed by summing circuit (21) to provide a signal V.sub.OUT that is absent of DC offset voltage errors that were present in the originally transmitted data signal. First and second resistors (36, 38) extract the common mode component of the input signal which may be subtracted from the V.sub.OUT signal for providing an error free true data output signal VTO.

Abstract: A circuit for asynchronously delaying an input signal whereby the precision of the time delay is proportional to the precision of the clock. A first circuit is coupled across a first capacitor for charging the first capacitor to a predetermined voltage when the clock is in a first logic state and discharging the first capacitor when the clock is in a second logic state. A peak-hold circuit having an input coupled to a first terminal of the first capacitor and an output signal at an output that provides a reference voltage representative of the peak voltage occurring at the input of the peak-hold circuit which is a function of the time interval the clock occupied the first logic state. A second circuit is coupled across a second capacitor for charging the second capacitor when the input signal is in a first logic state, and discharging the second capacitor when the input signal is in a second logic state.

Abstract: A voltage translator circuit generates a predetermined output voltage (e.g. one half of the supply voltage) in response to a predetermined input voltage. A pair of matched field effect transistors are coupled in series between first and second sources of supply voltage. The gate of the load transistor is coupled to a reference voltage, and the gate of the drive transistor is coupled to a source of input voltage. When both transistors are subject to the same operating conditions (at a predetermined input voltage level), their effective resistances become equal and the supply voltage is divided in half. The circuit does not depend for its operation upon precise threshold voltages of the devices as long as the devices are matched.