Abstract: A distributed digital imaging processing system having a number of processing units and circular FIFO buffers connected together using data transforming streams. Processing units read data from buffers using a transforming read streams. These read streams reorder the buffer data to form patches representing neighborhood pixels and may provide the same data multiple times. After processing a patch, a processing unit writes the resultant patch into a buffer using a transforming write stream which reorders the data into the storage format of the buffer. Several buffers can feed a single processor and one processor can feed several buffers. All the details of each data stream (buffer, current buffer location, patch size, access pattern) are stored in a table entry, along with a pointer to the data stream that it must follow in the buffer to avoid the hazards of reading and writing data out of order.

Abstract: An image is generated from a database of three-dimensional object data where each the objects is formed from at least one polygon having at least one edge. Successively determinations are made as to whether a particular one of the object polygons designated as the test polygon is not visible to an observer located at a predetermined location by virtue of being hidden by other objects in the database. If the test polygon is determined to be not visible, then it does not need to be rendered by an image renderer and may be discarded. The decision is made by successively selecting one of the three-dimensional object in the database. After an object is selected, each of the object polygon is selected to determining whether the polygon is occulted by another object.

Abstract: A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array, anode encoding logic circuits connected to the input registers, midpoint pipeline registers connected to the anode encoding logic circuits and pixel decoding logic circuits connected to the midpoint pipeline registers. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multi-anode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size.