Abstract: A virtual segmentation system and a method of operating the same. In one embodiment, the virtual segmentation system includes a protocol data unit receiver subsystem configured to (i) receive at least a portion of a protocol data unit and (ii) store the at least a portion of the protocol data unit in at least one block, and a virtual segmentation subsystem, associated with the protocol data unit receiver subsystem, configured to perform virtual segmentation on the protocol data unit by segmenting the at least one block when retrieved without reassembling an entirety of the protocol data unit.

Abstract: A method, data processing system, and computer program product are provided for retrieving access rules using a plurality of subtables. An incoming packet that includes fields of data is received from a network. A key is formed from the fields, the key includes a number of subkeys. The subkeys are selected and each of the selected subkeys is used to search a different subtable. If a subtable entry is a pointer, a next level subtable is searched until a failure or data is encountered. If a failure occurs, a default rule is applied. If data is encountered, the key is masked using a stored mask value. The resulting masked key is compared to a stored rule. If they match, the identified rule is applied, otherwise the default rule is applied.

Abstract: A locking mechanism to minimize access to a portion of a rack-mounted electronic device is provided. The locking mechanism includes a bar supported at one end to a first vertical post of the rack, and a locking member supported at a second end of the bar for locking to a second vertical post. In one embodiment, the bar is pivotally supported at the one end to the first post. The bar is movable between an open position where unimpeded access to a first portion of the electronic device is provided, and a closed position to restrict removal of components from the first portion of the electronic device. A clearance space may provided between the bar and the electronic device in the closed position to allow a user to access an electronic component to remove power from the component, but not to fully remove the component without unlocking the locking member.

Abstract: A processor includes a scheduler operative to schedule data blocks for transmission from a plurality of queues or other transmission elements, utilizing at least a first table and a second table. The first table may comprise at least first and second first-in first-out (FIFO) lists of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a first scheduling algorithm, such as a weighted fair queuing scheduling algorithm. The scheduler maintains a first table pointer identifying at least one of the first and second lists of the first table as having priority over the other of the first and second lists of the first table. The second table includes a plurality of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a second scheduling algorithm, such as a constant bit rate or variable bit rate scheduling algorithm.

Abstract: A processor includes scheduling circuitry for scheduling data blocks for transmission from multiple transmission elements, and traffic shaping circuitry coupled to the scheduling circuitry and operative to establish a traffic shaping requirement for the transmission of the data blocks from the transmission elements. The scheduling circuitry is configured for utilization of at least one time slot table which includes multiple locations, each corresponding to a transmission time slot. The scheduling circuitry is operative in conjunction with the time slot table to schedule the data blocks for transmission in a manner that substantially maintains the traffic shaping requirement established by the traffic shaping circuitry even in the presence of collisions between requests from the transmission elements for each of one or more of the time slots.

Abstract: In a communication system comprising a link layer device connectable to one or more physical layer devices, at least a given one of a plurality of ports of the one or more physical layer devices is designated as a port for which status information is to be requested by the link layer device on a more frequent basis than such information is to be requested for one or more other ports of the plurality of ports. The ports are then polled by the link layer device in accordance with a non-linear polling sequence such that the at least one designated port is polled more frequently than the one or more other ports. The designated port may comprise a port to which the link layer device transmits data in conjunction with a current data transfer. The non-linear polling sequence may thus be altered dynamically based on particular data transfers that are occurring between a link layer device and a physical layer device in a communication system.

Abstract: A method, data processing system, and computer program product are provided for retrieving access rules using a plurality of subtables. An incoming packet that includes fields of data is received from a network. A key is formed from the fields, the key includes a number of subkeys. The subkeys are selected and each of the selected subkeys is used to search a different subtable. If a subtable entry is a pointer, a next level subtable is searched until a failure or data is encountered. If a failure occurs, a default rule is applied. If data is encountered, the key is masked using a stored mask value. The resulting masked key is compared to a stored rule. If they match, the identified rule is applied, otherwise the default rule is applied.

Abstract: A processor includes scheduling circuitry and an associated interval computation element. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, and is configured for utilization of at least one time slot table in scheduling the data blocks for transmission. The interval computation element, which may be implemented as a script processor, is operative to determine an interval for transmission of one or more data blocks associated with corresponding locations in the time slot table. The transmission interval is adjustable under control of the interval computation element so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.

Abstract: A processor includes scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements. The scheduling circuitry has at least one time slot table accessible thereto, and is configured for utilization of the time slot table in scheduling the data blocks for transmission. The time slot table includes a plurality of locations, with each of the locations corresponding to a transmission time slot and being configurable for storing identifiers of at least two of the transmission elements. In an illustrative embodiment, a given one of the locations in the time slot table stores in a first portion thereof an identifier of a first one of the transmission elements that has requested transmission of a block of data in the corresponding time slot, and stores in a second portion thereof an identifier of a second one of the transmission elements that has requested transmission of a block of data in the corresponding time slot.

Abstract: A processor includes scheduling circuitry and a priority computation element associated with the scheduling circuitry. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, in accordance with a transmission priority established by the priority computation element. The priority computation element, which may be implemented as a script processor, is operative to determine a transmission priority for one or more constituent transmission elements in a specified group of such transmission elements. The group of transmission elements corresponds to a first level of an n-level hierarchy of transmission elements, with the constituent transmission elements corresponding to at least one lower level of the n-level hierarchy of transmission elements. The transmission priority is preferably made adjustable under software control so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.

Abstract: Techniques are disclosed for flexible allocation of address pins of an interface bus to particular sub-buses of the interface bus. The interface bus is between at least one physical layer device and a link layer device in a communication system. Each of the sub-buses has an interface block of the link layer device associated therewith, the interface bus being configurable to carry a composite address signal having a plurality of portions each associated with one of the address pins of the interface bus. The interface blocks of the link layer device are controlled such that each of at least a subset of the interface blocks utilizes only particular ones of the address pins that are controllably allocated to the associated sub-bus in accordance with configuration information stored in the link layer device. The composite address signal is generated as a combination of address outputs of the interface blocks.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: A process and architecture to simplify the implementation of a high-speed scheduler. A traditional packet based scheduler works the length of the packet. Instead, the present invention uses a transmit queue that determines how many times a portion of a packet needs to be transmitted independent of the process to modify or transform the packet. The packet could be an ATM cell, it could be a fabric cell, or it could be a portion of a frame-based transmission of the packet. As a result, the transmit queue need only determine how many times (times to transmit (TTT)) to schedule transmission of part of the packet. The determined TTT from the transit queue takes into account the packet-based modifications that will be performed on the packet. The TTT is used to determine how many cells the packet needs to be divided into. In another illustrative embodiment, the number of cells or the TTT is determined prior to adding or removing data from the packet.

Abstract: A virtual segmentation system for use with a routing switch processor and a method of operating the same. In one embodiment, the virtual segmentation system includes a protocol data unit receiver subsystem configured to receive at least a portion of a protocol data unit and assemble the protocol data unit. The virtual segmentation system further includes a virtual segmentation subsystem that is associated with the protocol data unit receiver subsystem and is configured to perform virtual segmentation on the protocol data unit.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: A processor includes scheduling circuitry and a priority computation element associated with the scheduling circuitry. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, in accordance with a transmission priority established by the priority computation element. The priority computation element, which may be implemented as a script processor, is operative to determine a transmission priority for one or more constituent transmission elements in a specified group of such transmission elements. The group of transmission elements corresponds to a first level of an n-level hierarchy of transmission elements, with the constituent transmission elements corresponding to at least one lower level of the n-level hierarchy of transmission elements. The transmission priority is preferably made adjustable under software control so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.

Abstract: A processor includes scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements. The scheduling circuitry has at least one time slot table accessible thereto, and is configured for utilization of the time slot table in scheduling the data blocks for transmission. The time slot table includes a plurality of locations, with each of the locations corresponding to a transmission time slot and being configurable for storing identifiers of at least two of the transmission elements. In an illustrative embodiment, a given one of the locations in the time slot table stores in a first portion thereof an identifier of a first one of the transmission elements that has requested transmission of a block of data in the corresponding time slot, and stores in a second portion thereof an identifier of a second one of the transmission elements that has requested transmission of a block of data in the corresponding time slot.

Abstract: A processor includes scheduling circuitry and an associated interval computation element. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, and is configured for utilization of at least one time slot table in scheduling the data blocks for transmission. The interval computation element, which may be implemented as a script processor, is operative to determine an interval for transmission of one or more data blocks associated with corresponding locations in the time slot table. The transmission interval is adjustable under control of the interval computation element so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.

Abstract: A processor includes scheduling circuitry for scheduling data blocks for transmission from multiple transmission elements, and traffic shaping circuitry coupled to the scheduling circuitry and operative to establish a traffic shaping requirement for the transmission of the data blocks from the transmission elements. The scheduling circuitry is configured for utilization of at least one time slot table which includes multiple locations, each corresponding to a transmission time slot. The scheduling circuitry is operative in conjunction with the time slot table to schedule the data blocks for transmission in a manner that substantially maintains the traffic shaping requirement established by the traffic shaping circuitry even in the presence of collisions between requests from the transmission elements for each of one or more of the time slots.

Abstract: A non-blocking crossbar for packet based networks and a method of operation thereof. In one embodiment, the non-blocking crossbar includes: (1) n inputs, n numbering at least two, (2) n outputs, each of the outputs having a destination first-in, first-out buffer (FIFO) and n crossbar FIFOs interposing corresponding ones of the n inputs and the destination FIFO, and (3) a scheduler configured to cause a packet to be transmitted from one of the inputs toward one of the outputs only when both the destination FIFO associated therewith and an interposing one of the crossbar FIFOs are available to contain the packet.