Abstract: A method is described for forming a high gain bipolar junction transistor in a optimized CMOS integrated circuit. The bipolar junction transistor comprises a compensated base region (130) which is formed by forming the p-well region (20) and the n-well region (30) in a common substrate region.

Abstract: A method is described for forming a high gain bipolar junction transistor in a optimized CMOS integrated circuit. The bipolar junction transistor comprises a compensated base region (130) which is formed by forming the p-well region (20) and the n-well region (30) in a common substrate region.

Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.

Abstract: In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.

Abstract: A device (10) for controlling current through a circuit has an antifuse material (18) separating a first conductor (12) and a second conductor (20). An insulating element (14) and another insulating element (16) further separate the first conductor (12) from the second conductor (20). The antifuse material (18) includes a dopant which raises the band gap and seals off paths in grain boundaries of the antifuse material (18) in order to limit leakage current from flowing between the first conductor (12) and the second conductor (20). When an interconnection is desired, a high voltage pulse is applied across the first conductor (12) and the second conductor (20) to initially break down the antifuse material (18). The breakdown of the antifuse material (18) causes a filament (22) to form between the first conductor (12) and the second conductor (20). The filament (22) creates a conduction path connecting the first conductor (12) and the second conductor (20) electrically together.

Abstract: Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions.

Abstract: A device (10) for controlling current through a circuit has an antifuse material (18) separating a first conductor (12) and a second conductor (20). An insulating element (14) and another insulating element (16) further separate the first conductor (12) from the second conductor (20). The antifuse material (18) includes a dopant which raises the band gap and seals off paths in grain boundaries of the antifuse material (18) in order to limit leakage current from flowing between the first conductor (12) and the second conductor (20). When an interconnection is desired, a high voltage pulse is applied across the first conductor (12) and the second conductor (20) to initially break down the antifuse material (18). The breakdown of the antifuse material (18) causes a filament (22) to form between the first conductor (12) and the second conductor (20). The filament (22) creates a conduction path connecting the first conductor (12) and the second conductor (20) electrically together.

Abstract: Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions.

Abstract: The described embodiments of the present invention provide a protective layer on the surface of silicided regions and methods for its formation. In the primary described embodiment, a titanium silicide layer is formed in integrated circuitry using self-aligned techniques. Local interconnection layers may be formed using biproducts of the self-aligned titanium disilicide formation. A layer of another siliciding metal, for example platinum, is then formed overall. The platinum layer is then subjected to an annealing step which causes a portion of the silicon in the titanium disilicide layers to react with the platinum to form platinum silicide. This platinum silicide layer is formed in a self-aligned manner on the surface of the silicided regions. The platinum silicide layer serves to protect the underlying titanium disilicide layer from subsequent etching steps of other harmful processing operations.

Abstract: A method for forming a self-aligned horizontal transistor includes the step of first defining a narrow base contact on an isolated N-tank (10) to define a first reference edge (41). A layer of sidewall oxide (40) is then disposed on the vertical wall of the base contact (34) to define a second reference edge (42). An emitter well (44) and a collector well (46) are then defined on either side of the contact with the vertical wall of the emitter well (44) aligned with the reference edge (42). A dopant material is then disposed adjacent the reference edge (42) and the dopant diffused into the substrate from a lateral direction to form a P-type base region (58) with a graded impurity profile. N-doped regions (64) and (66) are then formed in the emitter and collector wells to form the emitter and collector of the transistor.

Abstract: Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions.

Abstract: A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.

Abstract: Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions.

Abstract: A horizontal structure transistor is fabricated in a shallow epitaxial island which is completely surrounded by an insulator, such as oxide. The transistor has base and emitter regions which are diffused into the island from the same mask so that the base width is controllable and remains constant with respect to the emitter. A polysilicon base contact rests on top of the island and is isolated from the emitter and collector regions by an oxide layer. The horizontal structure transistor can easily be fabricated to include complementary bipolar transistors and complementary IGFET devices on the same substrate.

Abstract: The disclosure relates to a process station to precisely control the electrochemical anodization of specially prepared silicon substrates. Remotely placed voltage probes are utilized to monitor changes in the potential drop across the wafer as the anodization proceeds. As the available anodilizable area changes, the voltage drop across the wafer and hence the anodization current density is maintained at the desired value by the computer through the use of active feedback provided by these probes. Any desired anodization conditions can be programmed into the system using the system software, thereby adding an even greater degree of control over the process.

Abstract: A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.

Abstract: The disclosure relates to a method of forming an isolated semiconductor, preferably of the vertical bipolar variety, wherein a porous highly doped semiconductor layer is oxidized and, with a trench containing silicon oxide therein, forms a region encasing a moderately doped epitaxial layer disposed beneath a lightly doped epitaxial layer. The vertical bipolar device is formed in the moderately doped and lightly doped layers with the highly doped epitaxially deposited layer, which is now a silicon oxide layer, forming a portion of the isolation. The anodization of the highly doped layer takes place using an anodizing acid at a temperature of from about 0 to about 10 degrees C.

Abstract: Full oxide isolation of epitaxial islands can be accomplished by oxidizing suitably porous silicon. The porous silicon can be created by anodizing highly doped n+ silicon in hydroflouric acid. Lesser doped epitaxial regions will not become porous and will become isolated islands suitable for the fabrication of semiconductor devices.