Abstract: A voltage overshoot limiter having a detector circuit that looks at the node at which the undesirable overshoot would occur and provides a signal that is proportional to the unipolar rate of change of voltage at the node. This output is fed back to the first stage of the control circuit, error amplifier, etc. in such a manner as to reduce the rate of change of the circuit's nodal voltages to less than their slewing rates. By modifying the value of the detector's output for a given detected slew rate at the node, it is possible to reduce both its overshoot significantly and to reduce its unipolar rate of voltage change. The invention is described as being unipolar, that is, responding to rates of change of voltages which are either positive or negative, though bipolar implementations may be realized.

Abstract: A reverse current limited circuit configured to provide a reverse current limited low dropout voltage output. The reverse current limited circuit, coupled between a pair of terminals, comprises (i) a MOS pass transistor coupled in series between the first and second terminals, (ii) connection circuitry to connect the substrate of the MOS pass transistor to either one of the pair of terminals based on the relative magnitudes of the voltages measured on the pair of terminals, (iii) activation circuitry for turning on and off the MOS pass transistor based on the relative magnitudes of the voltages measured on the pair of terminals and (iv) comparison circuitry used to compare the voltages of the pair of terminals and to control the activation circuitry and the connection circuitry in response to the comparison made.

Abstract: A current limited low dropout voltage circuit for coupling between first and second power supply terminals and an output terminal for providing a current limited low dropout voltage output having a MOS pass transistor coupled in series between the first power supply terminal and the output terminal, a drive circuit coupled to the gate of the MOS pass transistor, circuitry for limiting the gate-source voltage of the MOS pass transistor to limit the maximum current therethrough to a first maximum current level when the voltage between the second power supply terminal and the output terminal is less than a predetermined value, and circuitry for limiting the gate-source voltage of the MOS pass transistor to limit the maximum current therethrough to a second maximum current level when the source to drain voltage of the MOS pass transistor is greater than a predetermined voltage difference and the voltage between the output terminal and the second power supply terminal is greater than the predetermined value, the s

Abstract: A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as a voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the circuit. Gain reduction devices are placed in the semiconductor substrate to collect minority carriers which would otherwise be injected into inherent parasitic four layer PNPN junction devices created as a result of the architecture of the circuit, to prevent latch-up of the four layer devices. In a preferred embodiment, an RS-232 receiver and transmitter are contained on the same monolithic integrated circuit as the dual charge pump power supply.

Abstract: A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period.

Abstract: The invention relates to an output circuit capable of producing an output signal which may be disabled, leaving the output terminal in a high impedance state capable of being driven externally to a voltage significantly outside the bounds of the output circuit power supply. The output circuit of the invention includes two terminals adapted to be connected to a power supply capable of providing a supply voltage. The output circuit includes an MOS transistor having a substrate, source and drain terminals and a gate, one of the source and drain terminals being coupled to one of the power supply terminals. A second transistor has three terminals including a control terminal and two other terminals, one of which is coupled to the other of the source and drain terminals of the MOS transistor, and the other of which is coupled to the other power supply terminal. An output terminal is coupled between the one terminal of the second transistor and the other of the source and drain terminals of the MOS transistor.

Abstract: An integrated off-line AC to DC power supply is disclosed. Alternating current (AC) line voltage is supplied (optionally) to an AC voltage to current converter and then (optionally) to a voltage limiter and rectifier which utilizes both MOS devices and inherent junction devices as either a full or half wave rectifier. The rectifier output is supplied to a series-pass junciton device voltage regulator or a regulator which has pre-set voltage output or user-selectable voltage output.

Abstract: A bipolar lateral pass-transistor is disclosed for use in MOS integrated circuits. The transistor includes a semiconductor substrate of a first conductivity type covered by an epitaxial layer, a first region of a second conductivity type disposed in the epitaxial layer at a first doping level to a depth of less than the depth of said epitaxial layer, a second region of said conductivity type spaced apart from and surrounding said first region and extending approximately the entire depth of said epitaxial layer having a doping level less than the first doping level and a third region of said second conductivity type spaced apart from and surrounding said second region and extending approximately the entire depth of said epitaxial layer having said first doping level at the surface of said epitaxial layer and said second doping level extending approximately to the bottom of said epitaxial layer.

Abstract: A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period.

Abstract: A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period.

Abstract: A full-wave rectifier circuit is disclosed having two AC input terminals each having connected to it the anode end of a diode equivalent device. The cathode ends of each of the diode equivalent devices are connected together to a positive DC output terminal. Each AC input terminal also has connected to it one end of a switching device. The other ends of each of the switching devices are connected together to a negative DC output terminal. The control means of the switching devices are connected such that only one conducts during any AC half cycle to provide a return path from the negative DC output terminal to the proper one of the two AC input terminals.

Abstract: A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period.

Abstract: An integrated off-line half-wave rectifier commonly connected to one side of the AC line at one of its output terminals is disclosed. An equivalent diode device passes current to the output during a positive AC input half cycle. A comparator senses the negative half cycle and turns on a switching device to conduct current between the two AC input terminals during that cycle.

Abstract: A power supply regulator in which a control pulse is generated at a position in time which varies in accordance with the voltage or current supplied by the power supply. The control pulse can be fed back across an isolation boundary with a simple device such as a pulse transformer with little or no loss of accuracy. Such a control signal is particularly adaptable to varying the duty cycles of transistor switch drive signals for switched-mode power supplies.

Abstract: A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period.

Abstract: A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period.

Abstract: A load circuit is provided with a backup power supply to power the essential functions of the load in the event that its primary power supply fails or is otherwise degraded. The positive terminals of both the primary power supply and the backup power supply, having a common negative reference, are input to a differential voltage comparator circuit. The output of the differential voltage comparator circuit controls a switching transistor located in a line between the primary power supply and the load, and when inverted by an inverter circuit, controls a second switching transistor located in a line between the backup power supply and the load. In operation, only the more positive of the primary power or the backup power supply voltages is provided to the load. The output of the inverter circuit is also available to indicate which of the two sources the power is applied to the load, and may be further used to disable non-essential portions of the load circuitry.

Abstract: An analog to digital converter is provided in which the converter output is scaled in accordance with the ratio of the clocking frequencies.

Abstract: A high speed charge balancing comparator in which, without loading or affecting its input, the internal nodes and output node are maintained at voltage levels at or very close to their autozero values until a time after the commencement of the compare phase such that the polarity of the voltage at the input charge balancing node is correct. The comparator is of the type for comparing two or more voltages including a gain stage having an input node responsive to the voltages, plural internal nodes and an output node, and a plurality of switches for sequencing the voltages to the input nodes during alternate autozero and compare phases. Switches maintain the gain stage internal nodes and output node at voltage levels close to their values during the autozero phase until a time after the commencement of the compare phase.

Abstract: A digitally switched analog signal conditioner comprising a plurality of pairs of input terminals, a junction, and an output terminal; a plurality of capacitors, first ends of the capacitors being connected to the junction; a plurality of switches being arranged in pairs, first ends of each pair being connected to the other ends of different ones of the capacitors, the other ends of each pair being connected to respective ones of a pair of input terminals, the switches of each pair being adapted to be operated alternatively; an amplifier having an input and an output, the input being operatively coupled to the junction; and a sample and hold circuit operatively coupled to the output of the amplifier for periodically sampling and holding the output, the output of the sampling and holding circuit being connected to one of the input terminals of one of the pairs of input terminals, the other of the terminals of the one pair of input terminals being connected to a point of reference potential.