Patents by Inventor David Bremaud

David Bremaud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9786807
    Abstract: A method to fabricate thin-film photovoltaic devices including a photovoltaic Cu(In,Ga)Se2 or equivalent ABC absorber layer, such as an ABC2 layer, deposited onto a back-contact layer characterized in that the method includes at least five deposition steps, during which the pair of third and fourth steps are sequentially repeatable, in the presence of at least one C element over one or more steps. In the first step at least one B element is deposited, followed in the second by deposition of A and B elements at a deposition rate ratio Ar/Br, in the third at a ratio Ar/Br lower than the previous, in the fourth at a ratio Ar/Br higher than the previous, and in the fifth depositing only B elements to achieve a final ratio A/B of total deposited elements.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: October 10, 2017
    Assignees: EMPA, FLISOM AG
    Inventors: Adrian Chirila, Ayodhya Nath Tiwari, Patrick Bloesch, Shiro Nishiwaki, David Bremaud
  • Patent number: 8928105
    Abstract: A method to fabricate monolithically-integrated optoelectronic module apparatuses (100) comprising at least two series-interconnected optoelectronic components (104, 106, 108). The method includes deposition and scribing on an insulating substrate or superstate (110) of a 3-layer stack in order (a, b, c) or (c, b, a) comprising: (a) back-contact electrodes (122, 124, 126, 128), (b) semiconductive layer (130), and (c) front-contact components (152, 154, 156, 158). Via holes (153, 155, 157) are drilled so that heat of the drilling process causes a metallization at the surface of said via holes that renders conductive the semi-conductive layer's surface (132, 134, 136, 138) of said via holes, thereby establishing series-interconnecting electrical paths between optoelectronic components (104, 106, 108) by connecting first front-contact components (154, 156) to second back-contact electrodes (124, 126).
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: January 6, 2015
    Assignee: Flisom AG
    Inventors: Roger Ziltener, Roland Kern, David Bremaud, Björn Keller
  • Publication number: 20140026956
    Abstract: A method to fabricate thin-film photovoltaic devices (100) comprising a photovoltaic Cu(In,Ga)Se2 or equivalent ABC absorber layer (130), such as an ABC2 layer, deposited onto a back-contact layer (120) characterized in that said method comprises at least five deposition steps, wherein the pair of third and fourth steps are sequentially repeatable, in the presence of at least one C element over one or more steps. In the first step at least one B element is deposited, followed in the second by deposition of A and B elements at a deposition rate ratio Ar/Br, in the third at a ratio Ar/Br lower than the previous, in the fourth at a ratio Ar/Br higher than the previous, and in the fifth depositing only B elements to achieve a final ratio A/B of total deposited elements.
    Type: Application
    Filed: April 17, 2012
    Publication date: January 30, 2014
    Applicants: EMPA, FLISOM AG
    Inventors: Adrian Chirila, Ayodhya Nath Tiwari, Patrick Bloesch, Shiro Nishiwaki, David Bremaud
  • Publication number: 20130056758
    Abstract: A method to fabricate monolithically-integrated optoelectronic module apparatuses (100) comprising at least two series-interconnected optoelectronic components (104, 106, 108). The method includes deposition and scribing on an insulating substrate or superstate (110) of a 3-layer stack in order (a, b, c) or (c, b, a) comprising: (a) back-contact electrodes (122, 124, 126, 128), (b) semiconductive layer (130), and (c) front-contact components (152, 154, 156, 158). Via holes (153, 155, 157) are drilled so that heat of the drilling process causes a metallization at the surface of said via holes that renders conductive the semi-conductive layer's surface (132, 134, 136, 138) of said via holes, thereby establishing series-interconnecting electrical paths between optoelectronic components (104, 106, 108) by connecting first front-contact components (154, 156) to second back-contact electrodes (124, 126).
    Type: Application
    Filed: May 27, 2011
    Publication date: March 7, 2013
    Applicant: FLISOM AG
    Inventors: Roger Ziltener, Roland Kern, David Bremaud, Björn Keller