Abstract: A system and method for testing signal interconnections using built-in self test (BIST). BIST functionality is designed into the various chips of a computer system. These chips include a transmit unit, a receive unit, a control logic unit, and a central logic unit. A control logic unit associated with a signal block (i.e. a group of signals) configures the signal block for either testing or normal operation. The central logic unit performs test pattern generation for all signal blocks on a given chip. Chips may act as either a master or slave chip during testing. When acting as a master chip, the transmit unit of the chip drives test patterns onto one or more signal lines. The receive unit of the slave chip returns a corresponding test pattern to the master chip after receiving the transmitted test pattern. A receive unit on the master chip receives the corresponding test patterns and performs verification. All tests occur at the operational clock speed of the computer system.

Abstract: Snooping is implemented on a split transaction snooping bus for a computer system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor.

Abstract: A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor.