Abstract: A data processor bus in which information is transferred between agents attached to the bus by issuing request packets that request data from an agent on the bus and reply packets that return data requested by a request packet. A control method mixes request-and-reply packets on the bus by determining the use of a next-bus cycle using arbitration, reply deferral, and specification lines and the state of a grant queue and a pipe queue in accordance with a specified protocol. A request is forced to take the next available bus cycle upon the condition that there is an agent identified in the great queue and the pipeline queue is not full. A reply packet is forced to take the next available bus cycle upon the condition that the pipeline queue is full. A reply packet is forced to take the next available bus cycle upon the condition that the grant queue is empty and the pipeline queue is not empty. Giving requests precedence over replies to allows the pipeline to be kept as full as possible.

Abstract: A computer system operative during an initialization phase to initialize modules of the system and during a subsequent non-initialization phase to transfer information between the initialized modules. A module bus (MB) has 32 signal lines beginning with a least-significant-bit signal line and ending with a most-significant-bit signal line. The bus (MB) connects the modules for data transfers after the initialization phase over bidirectional address lines and data lines connected to the module bus. A system support module (SSMI) starts the initialization phase by energizing an initialization signal line (INIT). In response, a processor (GDP) generates identification command information over the bus (MB) that continas a first data record and a second data record.

Abstract: When a load instruction is encountered, a read operation is sent to the bus control logic, the register is marked as busy, and execution proceeds to the next instruction. When an instruction is executed, it proceeds providing that its source and destination registers are not marked busy; otherwise the instruction is retried. When data are returned as the result of a read operation, the destination register(s) are marked as not busy.