Abstract: Systems and methods for testing a circuit are provided. In one example, a sequential device for use in a scan chain is described. The sequential device may include a scan input, a scan output and a functional data output. The functional data output may be coupled to the scan input and to the scan output. The functional data output may be coupled to the scan output via a delay buffer.

Abstract: Systems and methods for testing a circuit are provided. In one example, a sequential device for use in a scan chain is described. The sequential device may include a scan input, a scan output and a functional data output. The functional data output may be coupled to the scan input and to the scan output. The functional data output may be coupled to the scan output via a delay buffer.

Abstract: Systems and methods for testing a circuit are provided. In one example, a sequential device for use in a scan chain is described. The sequential device may include a scan input, a scan output and a functional data output. The functional data output may be coupled to the scan input and to the scan output. The functional data output may be coupled to the scan output via a delay buffer.

Abstract: A semiconductor device (400) and method are provided for multiplying a capacitance. A contact region (402) is formed in an island in a semiconductor substrate (499) bounded by an isolation region (403), producing the capacitance at the junction of the contact region (402). A dielectric layer (404) is formed over the semiconductor substrate (499) adjacent to the contact region (402). A contact layer (408) is formed over the dielectric layer (404) wherein an inversion layer (406) is formed under the contact layer (408), producing an inversion capacitance in response to an enabling signal. The inversion capacitance corresponds to a multiple of the capacitance.

Abstract: A system for determining the presence or absence of data on one or more data lines including a flip-flop for each data line with the output of each flip-flop connected to a NAND gate. The NAND gate is connected through an OR gate to two output flip-flops in series. The logic of the system is such that the output of the second of the two output flip-flops provides a signal level which is high or low depending on whether data is present on all of the data lines or one or more lines has no data.

Abstract: A frame error detection system for SONET which operates in both the OC-3 and OC-12 modes. The frame detection circuit operates by examining the incoming data bit stream, which is in parallel form, detecting A1 and A2 bytes and if, in the OC-3 mode, three consecutive A1 bytes are received, followed by three A2 bytes, then framing is correct. If one of these bytes is missing, then there is an error in framing. The bytes, as they are received and processed by the system, are stored in a series of flip-flops and the output logic signal therefrom is indicative of the framing condition as to whether it is correct or errored.

Abstract: An interrupt notice system for permitting individual ones of a plurality of operating devices to indicate to others that an interrupt of their operations is being initiated through transmitting an interrupt through a controller at a proper time. The controller provides for directing such interrupt, and for synchronizing the system.