Abstract: A solid state light source having first and second component light sources and an interface circuit and a method for making the same are disclosed. The first and second component light sources emit light having first and second color points on different sides of the black body radiation curve. The first and second component light sources include LEDs that emit light of a first wavelength and a layer of a light converting material that converts a portion of that light to light of a second wavelength. The interface circuit powers the first and second component light sources such that the solid state light source has a color point that is closer to the black body radiation curve than either the first or second color points. A third component light source can be included to expand the range of white color temperatures that can be reached by the light source.

Abstract: A solid state light source having first and second component light sources and an interface circuit and a method for making the same are disclosed. The first and second component light sources emit light having first and second color points on different sides of the black body radiation curve. The first and second component light sources include LEDs that emit light of a first wavelength and a layer of a light converting material that converts a portion of that light to light of a second wavelength. The interface circuit powers the first and second component light sources such that the solid state light source has a color point that is closer to the black body radiation curve than either the first or second color points. A third component light source can be included to expand the range of white color temperatures that can be reached by the light source.

Abstract: A content addressable memory (CAM) device for use in various sizes of systems while requiring minimal circuitry to enlarge the size of the prioritization circuitry. In smaller systems, the CAM device determines the highest priority CAM device having a match. In larger systems, an external logic device determines the highest priority CAM device having a match and then provides that information to each CAM device in the system. In both smaller and larger systems the CAM device determines if it is the highest priority CAM device having a match. In accordance with an exemplary embodiment of the invention, the CAM device needs only minimal programming to be configured to be utilized in either a larger or smaller system.

Abstract: The present invention provides a content addressable memory (CAM) device for use in various sizes of cascaded systems while requiring minimal circuitry to enlarge the size of the cascade. In smaller cascade systems, the CAM device determines the highest priority CAM device having a match. In larger cascade systems, an external logic device determines the highest priority CAM device having a match and then provides that information to each CAM device in the cascade. In both smaller and larger system, the CAM device determines if it is the highest priority CAM device having a match. In accordance with an exemplary embodiment of the invention, the CAM device needs only minimal programming to be configured to be utilized in either a larger or smaller cascade. Furthermore in another exemplary embodiment, the CAM device reviews the match signals received to determine if the match results are valid and therefore permits additional memory operations while waiting to provide the results of the first search.

Abstract: A method and apparatus are provided for performing hierarchical address translation by translating each ternary hierarchical address into a binary address and a binary priority mask and storing the binary addresses in the binary CAM. A binary search of the priority masks is then performed by searching the CAM with a priority mask and choosing a next priority mask depending on the results of the search of the CAM until a correct matching entry (i.e., the matching entry with the lowest hierarchical level) is found. This technique only requires log.sub.2 N searches of the CAM, where N is the number of hierarchical levels represented by the priority field. A method and apparatus are also provided for performing hierarchical address translation by storing table entries including a priority field in a ternary CAM and performing only a fixed number of searches of the CAM.

Abstract: Detection of the packet type of information packets received at a node in a packet based communications network is accomplished by comparing information from each received packet to a table (62) of possible packet types. After packet type has been identified, the corresponding packet is routed for processing based on type. For increased processing speed, the comparison with each of the entries in the table (62) can be performed substantially simultaneously. In one embodiment, a content addressable memory (CAM, 48) is utilized to store the table (62) information and to perform the required comparisons. In addition, wired OR means (50) is provided for use in reducing the total number of entries in the table (62). In a preferred embodiment, the cell types of asynchronous transfer mode (ATM) cells are detected.

Abstract: In accordance with the present invention, data is transmitted through a network in chunks. Chunks are self-describing units designed for high speed protocol processing. Packets act as envelopes for carrying chunks across a network. The self-describing nature of chunks allow them to be processed as they arrive at the receiver regardless of any misordering. The ability to process data without intermediate buffering for reordering or reassembly improves protocol processing performance. The chunks also distribute protocol data units control overhead over multiple packets.