Patents by Inventor David C. H. Cheng
David C. H. Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9237643Abstract: A circuit board structure including a dielectric layer, a fine circuit pattern and a patterned conductive layer is provided, wherein the fine circuit pattern is embedded in a surface of the dielectric layer, and the patterned conductive layer is disposed on another surface of the dielectric layer and protrudes therefrom.Type: GrantFiled: December 24, 2012Date of Patent: January 12, 2016Assignee: Unimicron Technology Corp.Inventors: Tsung-Yuan Chen, Shu-Sheng Chiang, David C. H. Cheng
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Patent number: 8365400Abstract: A circuit board structure comprising a composite layer, a fine circuit pattern and a patterned conductive layer is provided. The fine circuit pattern is inlaid in the composite layer, and the patterned conductive layer is disposed on a surface of the composite layer. After fine circuit grooves are formed on the surface of the composite layer, conductive material is filled into the grooves to form the fine circuit pattern inlaid in the composite layer. Since this fine circuit pattern has relatively fine line width and spacing, the circuit board structure has a higher wiring density.Type: GrantFiled: December 29, 2008Date of Patent: February 5, 2013Assignee: Unimicron Technology Corp.Inventors: Tsung-Yuan Chen, Shu-Sheng Chiang, David C. H. Cheng
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Patent number: 8288663Abstract: An electrical interconnecting structure suitable for a circuit board is provided. The electrical interconnecting structure includes a core, an ultra fine pattern, and a patterned conductive layer. The core has a surface, and the ultra fine pattern is inlaid in the surface of the core. The patterned conductive layer is disposed on the surface of the core and is partially connected to the ultra fine pattern. Since the ultra fine pattern of the electrical interconnecting structure is inlaid in the surface of the core and is partially connected to the patterned conductive layer located on the surface of the core.Type: GrantFiled: December 29, 2008Date of Patent: October 16, 2012Assignee: Unimicron Technology Corp.Inventors: Tsung-Yuan Chen, Shu-Sheng Chiang, David C. H. Cheng
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Publication number: 20120124830Abstract: A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad.Type: ApplicationFiled: January 31, 2012Publication date: May 24, 2012Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: David C. H. Cheng, Shao-Chien Lee, Tzyy-Jang Tseng
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Patent number: 8153472Abstract: An embedded chip package process is disclosed. A first substrate having a first patterned circuit layer is provided. A second substrate having a second patterned circuit layer is provided. A dielectric material layer is formed to cover the first patterned circuit layer. A compression process is performed to cover the second substrate over the dielectric material layer and the second patterned circuit layer is embed into the dielectric material layer. A curing process is performed to cure the dielectric material layer after the step of performing the compression process. At least a conductive plug through the dielectric material layer is formed to electrically connect the first patterned circuit layer to the second patterned circuit layer after the step of performing the curing process. The first substrate, the second substrate and a portion of the at least a conductive plug are removed after the step of forming the conductive through hole.Type: GrantFiled: December 6, 2010Date of Patent: April 10, 2012Assignee: Unimicron Technology Corp.Inventor: David C. H. Cheng
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Publication number: 20110076802Abstract: An embedded chip package process is disclosed. A first substrate having a first patterned circuit layer is provided. A second substrate having a second patterned circuit layer is provided. A dielectric material layer is formed to cover the first patterned circuit layer. A compression process is performed to cover the second substrate over the dielectric material layer and the second patterned circuit layer is embed into the dielectric material layer. A curing process is performed to cure the dielectric material layer after the step of performing the compression process. At least a conductive plug through the dielectric material layer is formed to electrically connect the first patterned circuit layer to the second patterned circuit layer after the step of performing the curing process. The first substrate, the second substrate and a portion of the at least a conductive plug are removed after the step of forming the conductive through hole.Type: ApplicationFiled: December 6, 2010Publication date: March 31, 2011Applicant: UNIMICRON TECHNOLOGY CORP.Inventor: David C. H. Cheng
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Patent number: 7888174Abstract: An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.Type: GrantFiled: September 21, 2008Date of Patent: February 15, 2011Assignee: Unimicron Technology Corp.Inventor: David C. H. Cheng
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Patent number: 7772703Abstract: A package substrate including a circuit board, a reinforcing plate and at least one conductive channel is provided. A first surface of the reinforcing plate is disposed on the circuit board for resisting the warpage of the circuit board. The reinforcing plate has an opening corresponding to a first contact of the circuit board exposed thereon. In addition, one end of the conductive channel is located in the opening and electrically connected to the first contact, and the other end of the conductive channel is located on a second surface of the reinforcing plate to form a bonding pad.Type: GrantFiled: September 20, 2006Date of Patent: August 10, 2010Assignee: Unimicron Technology Corp.Inventor: David C. H. Cheng
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Patent number: 7663249Abstract: An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.Type: GrantFiled: August 25, 2006Date of Patent: February 16, 2010Assignee: Unimicron Technology Corp.Inventor: David C. H. Cheng
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Publication number: 20090282674Abstract: An electrical interconnecting structure suitable for a circuit board is provided. The electrical interconnecting structure includes a core, an ultra fine pattern, and a patterned conductive layer. The core has a surface, and the ultra fine pattern is inlaid in the surface of the core. The patterned conductive layer is disposed on the surface of the core and is partially connected to the ultra fine pattern. Since the ultra fine pattern of the electrical interconnecting structure is inlaid in the surface of the core and is partially connected to the patterned conductive layer located on the surface of the core.Type: ApplicationFiled: December 29, 2008Publication date: November 19, 2009Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Tsung-Yuan Chen, Shu-Sheng Chiang, David C. H. Cheng
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Publication number: 20090284935Abstract: A circuit board structure comprising a composite layer, a fine circuit pattern and a patterned conductive layer is provided. The fine circuit pattern is inlaid in the composite layer, and the patterned conductive layer is disposed on a surface of the composite layer. After fine circuit grooves are formed on the surface of the composite layer, conductive material is filled into the grooves to form the fine circuit pattern inlaid in the composite layer. Since this fine circuit pattern has relatively fine line width and spacing, the circuit board structure has a higher wiring density.Type: ApplicationFiled: December 29, 2008Publication date: November 19, 2009Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Tsung-Yuan Chen, Shu-Sheng Chiang, David C. H. Cheng
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Publication number: 20090273907Abstract: A circuit board and process thereof are provided. The circuit board includes a dielectric layer, an active circuit, and two shielding circuits. The dielectric layer has an active surface. The active circuit is disposed on the active surface, and the shielding circuits are respectively disposed on two sides of the active circuit. The height of the shielding circuits is larger than the height of the active circuit.Type: ApplicationFiled: April 30, 2008Publication date: November 5, 2009Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Tsung-Yuan Chen, Tzyy-Jang Tseng, Shu-Sheng Chiang, David C. H. Cheng
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Publication number: 20090166059Abstract: A circuit board and process thereof are provided. The circuit board includes a dielectric layer, a main circuit, and two shielding circuits. The dielectric layer has an active surface. The main circuit is embedded in the dielectric layer and the shielding circuits are disposed at the dielectric layer. The shielding circuits are respectively located at two sides of the main circuit. The thickness of the shielding circuits is larger than the thickness of the main circuit.Type: ApplicationFiled: March 14, 2008Publication date: July 2, 2009Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: Tsung-Yuan Chen, Tzyy-Jang Tseng, Shu-Sheng Chiang, David C. H. Cheng
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Publication number: 20090144972Abstract: A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad.Type: ApplicationFiled: March 13, 2008Publication date: June 11, 2009Applicant: UNIMICRON TECHNOLOGY CORP.Inventors: David C. H. Cheng, Shao-Chien Lee, Tzyy-Jang Tseng
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Publication number: 20090023246Abstract: An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.Type: ApplicationFiled: September 21, 2008Publication date: January 22, 2009Applicant: UNIMICRON TECHNOLOGY CORP.Inventor: David C. H. Cheng
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Publication number: 20080036058Abstract: A package substrate including a circuit board, a reinforcing plate and at least one conductive channel is provided. A first surface of the reinforcing plate is disposed on the circuit board for resisting the warpage of the circuit board. The reinforcing plate has an opening corresponding to a first contact of the circuit board exposed thereon. In addition, one end of the conductive channel is located in the opening and electrically connected to the first contact, and the other end of the conductive channel is located on a second surface of the reinforcing plate to form a bonding pad.Type: ApplicationFiled: September 20, 2006Publication date: February 14, 2008Applicant: UNIMICRON TECHNOLOGY CORP.Inventor: David C. H. Cheng
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Publication number: 20080029890Abstract: An embedded chip package process is provided. First, a chip is connected to a first circuit layer on a carrier, and then a cover plate is pressed onto a dielectric material layer to make the chip embedded in the dielectric material layer so that a circuit board with an embedded chip is formed. The chip has at least a bump electrically connected to a bonding pad of the first circuit layer through a solder. With enhanced reliability and alignment in chip bonding, the flip-chip bonding process replaces the conventional method of Laser drilling and circuit fabrication.Type: ApplicationFiled: January 16, 2007Publication date: February 7, 2008Applicant: UNIMICRON TECHNOLOGY CORP.Inventor: David C. H. Cheng
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Publication number: 20070290366Abstract: An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.Type: ApplicationFiled: August 25, 2006Publication date: December 20, 2007Applicant: UNIMICRON TECHNOLOGY CORP.Inventor: David C. H. Cheng
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Patent number: 7284323Abstract: A fabrication process of a conductive column suitable for a fabrication of a circuit board. The circuit board comprises a dielectric layer. A first blind hole is formed in the dielectric layer from a second surface opposite to the first surface, wherein the blind end of the first blind hole connects to the blind end of the second blind hole. The first blind hole and the second blind hole constitute a through hole. The through hole is formed in an hourglass shape such that an inner diameter of the through hole near the first or the second surface is substantially larger than an inner diameter of the through hole near a middle portion of the through hole. A conductive material is filled in the though hole to form a conductive column.Type: GrantFiled: October 11, 2004Date of Patent: October 23, 2007Assignee: Unimicron Technology Corp.Inventor: David C. H. Cheng
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Publication number: 20060021794Abstract: A fabrication process of a conductive column suitable for a fabrication of a circuit board is provided. The circuit board comprises a dielectric layer. A first blind hole is formed in the dielectric layer from a first surface thereof, and a second blind hole is formed in the dielectric layer from a second surface opposite to the first surface, wherein the blind end of the first blind hole connects to the blind end of the second blind hole. The first blind hole and the second blind constitute a through hole and is formed in an hourglass shape such that an inner diameter of the through hole near to the first or the second surface is substantially larger than an inner diameter of the through hole near a middle portion of the through hole. A conductive material is filled in the through hole to form a conductive column.Type: ApplicationFiled: October 11, 2004Publication date: February 2, 2006Inventor: David C. H. Cheng