Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.

Abstract: A device for tomography of curved surfaces is disclosed including a source, an object having a curved surface, and a detector having a curved shape corresponding to the curved surface. Also disclosed are a method and apparatus for tomography of a curved surface in an object, that includes determining an expected distortion for each of a plurality of points in a projection of the curved surface, and correcting each of the plurality of points in the projection according to the expected distortion of that point.

Abstract: First and second clocked digital sources are provided in each of two data paths, and are clocked by respective direct and complementary clock pulses. The clocked outputs of these devices are directed to a multiplexer where the inter-leaved data path signals are recombined into a single output line. This multiplexer includes clocked transmission gates, the clock signals for which are shifted in time by 90° from the clock signals applied to the originating signal sources. The result is that additional time is made available for sampling the digital signals applied to the multiplexer.

Abstract: An integrated circuit includes a signal generator that receives an input signal having a frequency indicative of the operating frequency of the integrated circuit. The signal generator generates an intermediate signal having a magnitude that is dependent both upon the frequency of the input signal and on another factor such as a controlled resistance. A feedback circuit receives the intermediate signal, and provides control to the controlled resistance to maintain the magnitude of the intermediate signal within a predetermined range. Thus, the magnitude of the controlled resistance is adjusted based upon the operating frequency of the integrated circuit, and the feedback signal also is related to the operating frequency. The feedback signal may then be used to adjust the bias current, so that the bias current has a magnitude that is based upon a frequency at which the integrated circuit operates, resulting in more efficient power utilization with respect to operating frequency.

Abstract: An integrated circuit chip for determining when the frequency of a clock pulse input signal is below a predetermined threshold level and including a capacitor charged up by a current source to produce a linearly-varying ramp signal. The charging circuit includes two MOS transistors, one arranged as a resistor to control the charging current, the other arranged as a capacitor to be charged. When the oxide layer produced by the IC process for making the chips varies in thickness from one batch of chips to a subsequently produced batch, the effect on the charging of the MOS capacitor resulting from the change in capacitance of the previously produced chip is at least partly compensated for by the corresponding change in resistance of the MOS resistor, thereby tending to maintain the charging rate constant.

Abstract: A frequency-responsive integrated circuit (IC) for determining when the frequency of a clock pulse input signal is below a predetermined threshold level, the IC including a capacitor charged up at a nearly constant rate by a current source. If the capacitor voltage reaches one-third of the DC power voltage, and input pulses are received, the capacitor is discharged to start another charge-up cycle. If no input pulses were received, the capacitor continues to charge up until its voltage reaches two-thirds of the DC power voltage, at which point an output signal is produced indicating that the input frequency is below the predetermined threshold level.

Abstract: A current source DAC is provided including a plurality of current source cells arranged in an array of a plurality of columns and rows. Among the plurality of current source cells is a plurality of least significant bit cells, wherein each least significant bit cell includes at least one current source cell. The plurality of least significant bit cells includes current source cells from among a centrally located column of the array. Also among the plurality of current source cells is a plurality of most significant bit cells. Each most significant bit cell includes a plurality of current source cells electrically added together and physically located along a diagonal path across the columns and rows of the array. The current source cell include CMOS transistors. The physical layout and electrical connection scheme reduces DNL errors due to transistor process gradients.

Abstract: A cursor control system where the starting x-axis pixel position of the cursor pattern is determined by decoding the last two bits of the preloaded x-axis address (as determined by a manual control manipulated by the operator). This decoded data produces a signal for controlling the transmission gate multiplexer so as to determine the position where the cursor data stream is inserted into the video data stream.

Abstract: A frequency-responsive integrated circuit (IC) for determining when the frequency of a clock pulse input signal is below a predetermined threshold level, the IC including a capacitor charged up at a nearly constant rate by a current source. If the capacitor voltage reaches one-third of the DC power voltage, and input pulses are received, the capacitor is discharged to start another charge-up cycle. If no input pulses were received, the capacitor continues to charge up until its voltage reaches two-thirds of the DC power voltage, at which point an output signal is produced indicating that the input frequency is below the predetermined threshold level.

Abstract: Method for use in a CAD system whereby three-dimensional interferences among space-oriented objects can be rapidly determined by storing a reduced granularity of the design space in the form of a three-dimensional matrix having elements which represent identification numbers of objects which occupy the design space in the subcontinuum represented by the element. The element can be multidimensional or the element can refer to a table if more than one object occupies the associated subcontinuum. As objects are added to the drawing, the new objects are assigned unique index numbers which are stored in all the matrix elements corresponding to all the subcontinuums occupied by the object. Calculations for interference among pairs of objects need only be made between objects having their index number in a same element of the matrix.

Abstract: A ring-type oscillator with a plurality of delay cells including differential pairs of MOS transistors. Current sources supply current to each pair, and the magnitude of the current supplied is variable by a control voltage to alter the delay of the MOS devices, thereby to alter the frequency of oscillation. Each delay cell MOS device is connected in series with another MOS device biased into its linear region to act as a load resistance. This load is variable by the control voltage so as to tend to maintain the gain of the delay cells constant with changes in frequency of oscillation.

Abstract: A circuit for protecting an IC against electrostatic discharge includes a npn transistor having its collector connected to a first I/O pad and its emitter connected to VSS. A zener diode has its cathode connected to the first I/O pad, its anode connected both to the base of the npn transistor and to a first resistor. The other end of the resistor is connected to VSS.

Abstract: A current-output CMOS DAC with a compensation circuit to increase output impedance. The circuit includes an auxiliary MOS current source matched to at least one of the DAC bit-current sources. A comparator compares the drain voltage of the main MOS current source (which is connected to an external reference current source I.sub.ref) with the drain voltage of the auxiliary current source. The output of the comparator controls the magnitude and sign of a correction current which is directed to the main current source transistor and thereby alters the bit-current output to reduce the ouput sensitivity to changed conditions.

Abstract: A high resolution laminography system for the inspection of integrated circuits wherein a beam of highly focused electrons is traced in a circular pattern on a flat target within a vacuum chamber. The target converts the electron beam into X-rays, so that a source of X-rays is produced which rotates in synchronization with a rotating detector assembly. An object is placed within the vacuum chamber, between the X-ray source and the detector so that an X-ray cross sectional image of a cutting plane of the object is produced. A computer and feedback system controls image acquisition and an automated positioning system. The computer system can also operate under program control to automatically analyze data, measure characteristics of the object under inspection, and make decisions regarding the acceptability of the object's quality.

Abstract: A pulsed precision x-ray source includes a miniaturized internally self-shielding x-ray tube and an integral generator contained in a hand-held housing for generating timed bursts of x-ray having regulated energy level. A control grid and focus electrode within the tube enable precise on-off control of an electron beam directed to an x-ray emitting anode. The integral generator system includes an elongated, U-shaped unitary, molded plastic block mounted in the housing and includes a high voltage transformer having primary and secondary annular windings encased in a transformer portion of the block defining a central opening outside of the block for receiving a transformer core therethrough and, a capacitor-diode voltage multiplier stack connected to the secondary winding and having a positive node connectable to the anode and a negative node connectable to the cathode.

Abstract: A ball valve having improved inherent rangeability comprises a floating ball of conventional design that is rotatable through substantially 90.degree. between a pair of seats respectively located adjacent the upstream and downstream sides of the valve within a valve housing. At least one of the seats is a one-piece lubricant-impregnated metal seat configured to provide a concave central surface portion that makes full-face direct sealing contact with the ball, and which defines multiple spaced holes that extend through the seat to increase the fluid-to-metal contact of fluid passing through the seat thereby to reduce the pressure between the upstream and downstream sides of the valve. The pattern of holes may be such as to cause the valve to exhibit an equal percentage of flow characteristic for at least a portion of the ball rotation and/or a linear flow characteristic for at least a portion of the ball rotation.

Abstract: Graphics display system having a moving cursor, such as a cursor, for selecting a displayed entity with the capability of determining which one of several lower level entities in the vicinity of the cursor is to be selected. The correlation of a cursor with a entity intended to be selected is performed by calculating an index that does not represent the actual distance, which is time consuming, but rather represents a value, more quickly calculated, such that the size order among the indices is the same as the size order of the distances they represent.

Abstract: Graphics display system having a moving cursor, such as a cursor, for selecting a displayed entity. The correlation of a cursor with an entity intended to be selected is performed by storing a unique tag assigned to each entity in a cell in a correlation array related to a pel or group of pels corresponding to locations in a bit map of the pels comprising the entity. The x,y coordinates of the cursor are converted into a cell number corresponding to the bit map locations matching such x,y coordinates. The entity tag is then retrieved from the addressed cell.