Abstract: Embodiments are provided for a quaternary decoder that includes a plurality of decoder circuits, each decoder circuit coupled to a respective input line of a plurality of quaternary interface lines and to a respective pair of binary output lines; and a control logic circuit having a plurality of control signal lines coupled to each of the plurality of decoder circuits, the control logic circuit configured to: output a first sequence of logic levels, and output a second sequence of logic levels after the first sequence is complete; wherein at a time after the second sequence is complete, each decoder circuit is configured to output a pair of binary data values that correspond to a quaternary state of the respective input line, the quaternary state being one of four quaternary states including a logic high state, a logic low state, a floating state, and a tie-back state.

Abstract: A method and apparatus for providing serially shifted data to a plurality of registers (51 through 56) begins by providing an enable signal (14). A first time portion of the enable signal (14) is either asserted or pulsed in order to provide a bank select control signal to a bank select circuit (74). After providing the bank select information, the enable (14) is activated in order to enable the storage of serial input data within a register (40). While data is being provided via a data input (16) to the register (40), a monitoring circuit (72) is recording the number of clocks (12) required to provide the entire sequence data into the register (40). A combination of the decoding information provided by the bank select circuit (74) and the monitoring circuit (72) allows one of a plurality of registers to be written with the data from register (40) even when the registers (51 through 56) are of a same size.