Abstract: A transaction analyzer, for use in conjunction with a data acquisition system having a probe for accessing binary data, i.e. address and control signals appearing at the terminals of an operating microprocessor, determines the type of processor transaction occurring based on sequences of state changes occurring on a selected set of the control signals so accessed. The transaction analyzer then generates a binary number representing the transaction type which may be acquired by the acquisition system in conjunction with the data accessed by the probe. The transaction analyzer, which uses an asychronous state machine, also generates control signals used by the acquisition system to clock data storage along with a signal to control the direction of flow of data signals between the processor and the acquisition system.

Abstract: A variable tracking word recognizer generates an indicating signal when a microprocessor has accessed a memory stack location storing a dynamically addressed variable, the address of the variable being the sum of a dynamically assigned base address of the memory stack and a known address offset where the variable is stored on the stack in relation to the base address. The variable tracking word recognizer stores the dynamically assigned base address, when determined by a space allocation subroutine of a program running on the microprocessor, and then monitors the addresses subsequently appearing on the microprocessor address bus, generating the indicating signal when the current address matches the combination of stored base address and known address offset.

Abstract: A probe for a logic analyzer includes a replacement plug assembly comprising those portions of probe equipment which must be specifically adapted to accommodate a selected microprocessor, and a buffer probe assembly comprising those portions of probe equipment which are adapted for use with a wide variety of microprocessors. The replacement plug assembly and the buffer probe assembly are mechanically joined and electrically coupled by a square pin connector so that the replacement plug assembly may be removed from the probe and replaced with a differently configured replacement plug assembly when a different microprocessor is to be probed. Thus only a portion of the probe is changed to retarget the probe for different microprocessors.

Abstract: An input apparatus for a multi-channel device, such as a logic analyzer, is disclosed, the input apparatus providing the multi-channel device with a programmable set-up and hold feature. The multi-channel device acquires a logic signal from a product under test, the logic signal having associated therewith an actual set-up and hold time with respect to an external clock signal. The actual set-up and hold times are entered into the multi-channel device via a keyboard and a display. The device has stored therein a desired set-up and hold time required by the logic signal relative to the external clock signal. In accordance with the actual and the desired set-up and hold times, the multi-channel device changes the relative orientation of the acquired logic signal with respect to the external clock signal, along the time axis until the set-up and hold times of the acquired logic signal are changed from the actual value to the desired value.

Abstract: A logic analyzer for measuring individually a plurality of logic signals transmitted via a multiplexed digital bus in a time-sharing manner is disclosed. First and second memory circuits store respectively first and second logic signals of the multiplexed digital bus in accordance with first and second strobe signals synchronized with the first and second logic signals.

Abstract: A logic analyzer which can simultaneously measure one block of input data in detail and the same or another block of input data in rough form is disclosed. The logic analyzer comprises first and second sections each including a memory circuit to store the input data and a word recognizer to detect the desired trigger word from the input data. These first and second sections receive different clocks having different rates, and the second memory circuit stores the first clock applied to said first section for recognizing the time relationship of these clock signals. A counter counts the first clock in accordance with the outputs from the first and second word recognizers for recognizing the time relationship of the first and second trigger words.