Abstract: A phased array waveguide antenna having a plurality of longitudinally extending parallel waveguides arranged in rows and columns, and electrically controlled phase shifter strips disposed in longitudinally extending slots centrally located in respective columns of waveguides. The electrically controlled phase shifter strips include conductive patches that are selectively conductively connected together by microwave diodes to provide for variable susceptances.

Abstract: A command guidance weapon system comprising a radar target tracking system, and a weapon with small thrusters mounted on the periphery thereof and with a small beacon transmitter which is tracked by a ground-based fire control system is disclosed. A rapid terminal maneuver is executed by the weapon at an appropriate point in the trajectory of the weapon by sequentially firing the small thrusters. The angular orientation of the weapon is obtained by canting a polarized antenna, located on the rear of the weapon, with respect to the longitudinal axis of the weapon so that the signal transmitted from the weapon to the ground-based fire control system is modulated. The fire control system computes the precise time, based upon the angular orientation of the weapon and the distance between the weapon and the target, to initiate the terminal maneuver by the weapon, and sends a command signal to the weapon.

Abstract: Control for overlapping instruction execution in an arithmetic unit is provided by stepping a sequence of instructions through a plurality of registers connected in cascade and separately decoding each instruction in a register for control of a corresponding stage in one or more data processing paths, each comprising stages through which data being processed is stepped, each stage corresponding to only one register of the control pipeline. The output of the decoder of each instruction register controls the required operations in the corresponding stage of the data pipeline. Automatically indexed indirect addressing is provided by use of pointers for data sources and destinations as required in the execution of every instruction in order to facilitate highly iterative and structured operations on blocks or arrays of data.

Abstract: Control for overlapping instruction execution in an arithmetic unit is provided by stepping a sequence of instructions through a plurality of registers connected in cascade and separately decoding each instruction in a register for control of a corresponding stage in one or more data processing paths, each comprising stages through which data being processed is stepped, each stage corresponding to only one register of the control pipeline. The output of the decoder of each instruction register controls the required operations in the corresponding stage of the data pipeline. Automatically indexed indirect addressing is provided by use of pointers for data sources and destinations as required in the execution of every instruction in order to facilitate highly iterative and structured operations on blocks or arrays of data.