Patents by Inventor David Da-Wei Lin
David Da-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11569806Abstract: Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.Type: GrantFiled: February 2, 2022Date of Patent: January 31, 2023Assignee: Synopsys, Inc.Inventors: Kuan Zhou, David Da-Wei Lin, Vladimir Zlatkovic, Shefali Walia, Youssef Mamdouh El-Toukhy, Abdelrahman Alaa Gouda, Alexander A. Alexeyev
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Patent number: 11456052Abstract: Systems and methods of write deskew training for ×4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.Type: GrantFiled: December 10, 2020Date of Patent: September 27, 2022Assignee: Marvell Asia Pte, Ltd.Inventor: David Da Wei Lin
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Publication number: 20220247398Abstract: Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.Type: ApplicationFiled: February 2, 2022Publication date: August 4, 2022Inventors: Kuan ZHOU, David Da-Wei LIN, Vladimir ZLATKOVIC, Shefali WALIA, Youssef Mamdouh EL-TOUKHY, Abdelrahman Alaa GOUDA, Alexander A. ALEXEYEV
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Patent number: 10892032Abstract: System and method of write deskew training for ×4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.Type: GrantFiled: August 8, 2019Date of Patent: January 12, 2021Assignee: Marvell Asia Pte, Ltd.Inventor: David Da Wei Lin
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Patent number: 10649025Abstract: A byte lane of an integrated circuit including two data strobe loopback paths that allow external test signals to flow in and out of the integrated circuit through data strobe pins in two opposite directions. The integrated circuit includes a Feed Forward Equalization (FFE) path configured to send FFE signals output from the FFE logic via a transmitter set to a first data strobe interface during a normal operation. In a loopback test mode operation, a test signal can be supplied from a second data strobe interface and output to the first data strobe interface by reusing the FFE path. The second loopback path conversely allows a test signal to be routed from the first data strobe interface to the second.Type: GrantFiled: March 23, 2018Date of Patent: May 12, 2020Assignee: Cavium, LLC.Inventors: David Da-Wei Lin, Edward Wade Thoenes
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Patent number: 10497413Abstract: System and method of read deskew training for ×4 mode memory control interface configurations. A read deskew training process includes aligning the two strobe signals serving one byte before deskewing the data bits against their corresponding strobe signals. A deskew setting of a variable delay line associated with the second strobe signal is adjusted to align the second strobe signal with reference to the first strobe signal. By aligning the two strobe signals with respect to each other, the read leveling settings can be common within the byte even the two DQS signals are transmitted to or received from two different memory storage devices.Type: GrantFiled: July 19, 2018Date of Patent: December 3, 2019Assignee: CAVIUM, LLCInventor: David Da Wei Lin
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Publication number: 20190293709Abstract: A byte lane of an integrated circuit including two data strobe loopback paths that allow external test signals to flow in and out of the integrated circuit through data strobe pins in two opposite directions. The integrated circuit includes a Feed Forward Equalization (FFE) path configured to send FFE signals output from the FFE logic via a transmitter set to a first data strobe interface during a normal operation. In a loopback test mode operation, a test signal can be supplied from a second data strobe interface and output to the first data strobe interface by reusing the FFE path. The second loopback path conversely allows a test signal to be routed from the first data strobe interface to the second.Type: ApplicationFiled: March 23, 2018Publication date: September 26, 2019Inventors: David Da-Wei LIN, Edward Wade THOENES
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Patent number: 10418125Abstract: System and method of write deskew training for ×4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.Type: GrantFiled: July 19, 2018Date of Patent: September 17, 2019Assignee: Marvell SemiconductorInventor: David Da Wei Lin
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Patent number: 9613679Abstract: A controller includes first and second functional units, first and second clock-signal sources that provide corresponding first and second clock signals that drive the first and second functional units respectively. The second clock-signal generates its second clock-signal based on the first clock-signal. The clock-retardation unit dynamically causes the second clock-signal to have a target time-domain offset relative to the first clock-signal.Type: GrantFiled: November 14, 2014Date of Patent: April 4, 2017Assignee: Cavium, Inc.Inventors: David Da-Wei Lin, Edward Wade Thoenes
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Patent number: 9601181Abstract: An apparatus for data processing includes first and second functional units driven by corresponding first and second clock-signal sources, and a clock-retardation unit. The clock-retardation unit is configured to cause the second clock-signal to sustain a temporal offset that causes an offset between the first and second clock-signals to step toward a target time-domain offset between the first and second clock-signals.Type: GrantFiled: November 14, 2014Date of Patent: March 21, 2017Assignee: Cavium, Inc.Inventors: David Da-Wei Lin, Edward Wade Thoenes, Vasudevan Kandadi
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Patent number: 9570128Abstract: An apparatus for controlling memory includes a memory controller, and an interface to data lines connecting it to memory. Each line carries a signal that corresponds to a bit to be written to memory. The interface includes, for each line, circuitry for transmitting a bit to memory via the line, and a data de-skewer. For each line, the de-skewer receives a first data signal that represents a bit to be written. Each line has an inherent skew. The de-skewer generates a second data signal by applying a skew to the first. A selected extent of skew increases a likelihood of sampling the second data signal during a data-valid window thereof. The same de-skewer receives and skews a first data bit read from the memory.Type: GrantFiled: November 14, 2014Date of Patent: February 14, 2017Assignee: Cavium, Inc.Inventors: David Da-Wei Lin, Edward Wade Thoenes, Thucydides Xanthopoulos
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Patent number: 9502099Abstract: A method for controlling a memory includes causing a data de-skewer to operate in a writing mode, at the data de-skewer, receiving a first signal, and skewing the first data signal by a first compensation skew, causing the data de-skewer to operate in a reading mode, at the data de-skewer, receiving a second signal, and skewing the second signal by a second compensation skew, wherein the first signal is representative of a bit from a byte that is to be written to the memory, and wherein the second signal is representative of a bit from a byte that has been read from the memory.Type: GrantFiled: November 14, 2014Date of Patent: November 22, 2016Assignee: Cavium, Inc.Inventors: David Da-Wei Lin, Edward Wade Thoenes
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Publication number: 20160141018Abstract: A method for controlling a memory includes causing a data de-skewer to operate in a writing mode, at the data de-skewer, receiving a first signal, and skewing the first data signal by a first compensation skew, causing the data de-skewer to operate in a reading mode, at the data de-skewer, receiving a second signal, and skewing the second signal by a second compensation skew, wherein the first signal is representative of a bit from a byte that is to be written to the memory, and wherein the second signal is representative of a bit from a byte that has been read from the memory.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: David Da-Wei Lin, Edward Wade Thoenes
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Publication number: 20160141017Abstract: A controller includes first and second functional units, first and second clock-signal sources that provide corresponding first and second clock signals that drive the first and second functional units respectively. The second clock-signal generates its second clock-signal based on the first clock-signal. The clock-retardation unit dynamically causes the second clock-signal to have a target time-domain offset relative to the first clock-signal.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: David Da-Wei Lin, Edward Wade Thoenes
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Publication number: 20160141016Abstract: An apparatus for data processing includes first and second functional units driven by corresponding first and second clock-signal sources, and a clock-retardation unit. The clock-retardation unit is configured to cause the second clock-signal to sustain a temporal offset that causes an offset between the first and second clock-signals to step toward a target time-domain offset between the first and second clock-signals.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: David Da-Wei Lin, Edward Wade Thoenes, Vasudevan Kandadi