Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to access control mechanisms used to protect isolated memory regions. Embodiments described herein enable a distributed and efficient register structure enabling system providers to reduce cost and improve system performance while preventing malicious devices from accessing isolated memory regions. Isolated memory region access control registers are distributed through multiple access points or bridges but each may be optimized and minimized to allow fast and efficient access control. Other embodiments may be described and/or claimed.

Abstract: An embodiment of an integrated circuit may comprise a management controller and circuitry communicatively coupled to the management controller, the circuitry to apply two or more respective controls to statistical data from two or more respective data sources in accordance with respective configuration information for each data source, and store the statistical data in a memory in accordance with the applied two or more controls. Other embodiments are disclosed and claimed.

Abstract: A secure memory card with encryption capabilities comprises various life cycle states that allow for testing of the hardware and software of the card in certain of the states. The testing mechanisms are disabled in certain other of the states thus closing potential back doors to secure data and cryptographic keys. Controlled availability and generation of the keys required for encryption and decryption of data is such that even if back doors are accessed that previously encrypted data is impossible to decrypt and thus worthless even if a back door is found and maliciously pried open.

Abstract: A secure memory card with encryption capabilities comprises various life cycle states that allow for testing of the hardware and software of the card in certain of the states. The testing mechanisms are disabled in certain other of the states thus closing potential back doors to secure data and cryptographic keys. Controlled availability and generation of the keys required for encryption and decryption of data is such that even if back doors are accessed that previously encrypted data is impossible to decrypt and thus worthless even if a back door is found and maliciously pried open.

Abstract: Some demonstrative embodiments of the invention include a method, device and/or system of selectively allowing a host processor to access a host-executable code. A host apparatus may include, for example, a host processor; and a protected memory module comprising: a memory to maintain a host-executable code to be executed by the host processor; and a memory controller to authenticate the host-executable code, and to selectively allow the host processor to access the host-executable code based on an authenticity of the host-executable code. Other embodiments are described and claimed.

Abstract: A secure memory card with encryption capabilities comprises various life cycle states that allow for testing of the hardware and software of the card in certain of the states. The testing mechanisms are disabled in certain other of the states thus closing potential back doors to secure data and cryptographic keys. Controlled availability and generation of the keys required for encryption and decryption of data is such that even if back doors are accessed that previously encrypted data is impossible to decrypt and thus worthless even if a back door is found and maliciously pried open.

Abstract: The throughput of the memory system is improved where data in a data stream is cryptographically processed by a circuit without involving intimately any controller. The data stream is preferably controlled so that it has a selected data source among a plurality of sources and a selected destination among a plurality of destinations, all without involving the controller. The cryptographic circuit may preferably be configured to enable the processing of multiple pages, selection of one or more cryptographic algorithms among a plurality of algorithms to encryption and/or decryption without involving a controller, and to process data cryptographically in multiple successive stages without involvement of the controller. For a memory system cryptographically processing data from multiple data streams in an interleaved manner, when a session is interrupted, security configuration information may be lost so that it may become impossible to continue the process when the session is resumed.

Abstract: Some demonstrative embodiments of the invention include a method, device and/or system of selectively allowing a host processor to access a host-executable code. A host apparatus may include, for example, a host processor; and a protected memory module comprising: a memory to maintain a host-executable code to be executed by the host processor; and a memory controller to authenticate the host-executable code, and to selectively allow the host processor to access the host-executable code based on an authenticity of the host-executable code. Other embodiments are described and claimed.

Abstract: Some demonstrative embodiments of the invention include a method, device and/or system to encrypt and/or decrypt data. In one demonstrative embodiment, the device may include, for example, a storage; and an encryption/decryption module to: receive externally-encrypted data to be stored in the storage, wherein the externally-encrypted data is encrypted using an external key; decrypt the externally-encrypted data using the external key to generate decrypted data; and encrypt the decrypted data using a securely maintained internal key to generate internally-encrypted data. Other embodiments are described and claimed.

Abstract: The throughput of the memory system is improved where data in a data stream is cryptographically processed by a circuit without involving intimately any controller. The data stream is preferably controlled so that it has a selected data source among a plurality of sources and a selected destination among a plurality of destinations, all without involving the controller. The cryptographic circuit may preferably be configured to enable the processing of multiple pages, selection of one or more cryptographic algorithms among a plurality of algorithms to encryption and/or decryption without involving a controller, and to process data cryptographically in multiple successive stages without involvement of the controller. For a memory system cryptographically processing data from multiple data streams in an interleaved manner, when a session is interrupted, security configuration information may be lost so that it may become impossible to continue the process when the session is resumed.

Abstract: A secure memory card with encryption capabilities comprises various life cycle states that allow for testing of the hardware and software of the card in certain of the states. The testing mechanisms are disabled in certain other of the states thus closing potential back doors to secure data and cryptographic keys. Controlled availability and generation of the keys required for encryption and decryption of data is such that even if back doors are accessed that previously encrypted data is impossible to decrypt and thus worthless even if a back door is found and maliciously pried open.

Abstract: Decoding an encoded block of data is accomplished by partitioning the block into a first and a second sub-block and performing forward and backward iterative calculations on the sub-blocks in separate processes. Based on results of the iterative calculations an output matrix may be calculated for each sub-block. The outputs may be combined.

Abstract: Decoding an encoded block of data may be accomplished by partitioning the block into a first and a second sub-block and performing forward and backward iterative calculations on the sub-blocks in separate processes. Based on results of the iterative calculations an output matrix may be calculated for each sub-block. The outputs may be combined.

Abstract: A flash memory system having a controller and a flash memory device for providing BIOS, operating system and user storage capabilities is provided. According to exemplary embodiments of the present invention, flash memory systems can be designed as integrated circuit packages which are pin compatible with conventional ROM BIOS chips so that existing systems can be readily upgraded without extensive modifications.

Abstract: A flash memory system having a controller and a flash memory device for providing BIOS, operating system and user storage capabilities is described. According to exemplary embodiments of the present invention, flash memory systems can be designed as integrated circuit packages which are pin compatible with conventional ROM BIOS chips so that existing systems can be readily upgraded without extensive modifications.