Patents by Inventor David Durham

David Durham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190087586
    Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 21, 2019
    Inventors: Francis X. McKEEN, Carlos V. ROZAS, Uday R. SAVAGAONKAR, Simon P. JOHNSON, Vincent SCARLATA, Michael A. GOLDSMITH, Ernie BRICKELL, Jiang Tao LI, Howard C. HERBERT, Prashant DEWAN, Stephen J. TOLOPKA, Gilbert NEIGER, David DURHAM, Gary GRAUNKE, Bernard LINT, Don A. VAN DYKE, Joseph CIHULA, Stalinselvaraj JEYASINGH, Stephen R. VAN DOREN, Dion RODGERS, John GARNEY, Asher ALTMAN
  • Publication number: 20190050283
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if an access request (e.g., a read or write request) to a memory location would result in an integrity failure and, if so determined, read previous data from the memory location, set an indicator to indicate the integrity failure, and store the previous data together with the indicator and previous authentication information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: July 27, 2018
    Publication date: February 14, 2019
    Applicant: Intel Corporation
    Inventors: David Durham, Siddhartha Chhabra, Kai Cong, Ron Gabor
  • Publication number: 20190044973
    Abstract: The present disclosure is directed to systems and methods for providing protection against replay attacks on memory, by refreshing or updating encryption keys. The disclosed replay protected computing system may employ encryption refresh of memory so that unauthorized copies of data are usable for a limited amount of time (e.g., 500 milliseconds or less). The replay protected computing system initially encrypts protected data prior to storage in memory. After a predetermined time or after a number of memory accesses have occurred, the replay protected computing system decrypts the data with the existing key and re-encrypts data with a new key. Unauthorized copies of data (such as those made by an adversary system/program) are not refreshed with subsequent new keys. When an adversary program attempts to use the unauthorized copies of data, the unauthorized copies of data are decrypted with the incorrect keys, which renders the decrypted data unintelligible.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Sergej Deutsch, David Durham, Karanvir Grewal, Rajat Agarwal
  • Publication number: 20190042734
    Abstract: Logic may implement implicit integrity techniques to maintain integrity of data. Logic may perform operations on data stored in main memory, cache, flash, data storage, or any other memory. Logic may perform more than one pattern check to determine repetitions of entities within the data. Logic may determine entropy index values and/or Boolean values and/or may compare the results to threshold values to determine if a data unit is valid. Logic may merge a tag with the data unit without expanding the data unit to create an encoded data unit. Logic may decode and process the encoded data unit to determine the data unit and the tag. Logic may determine value histograms for two or more entities, determine a sum of repetitions of the two or more entities, and compare the sum to a threshold value. Logic may determine that a data unit is valid or is corrupted.
    Type: Application
    Filed: December 20, 2017
    Publication date: February 7, 2019
    Inventors: Michael Kounavis, David Durham, Sergej Deutsch, Saeedeh Komijani, Amitabh Das
  • Publication number: 20190021446
    Abstract: A protective footwear includes a foot engagement portion, a lower-leg engagement portion, and a cable closure system. The lower-leg engagement portion defines a cable end interface and a buckle interface. The cable closure system is configured to facilitate at least partially securing the protective footwear to a leg of a wearer. The cable closure system includes a buckle assembly configured to releasably couple to the buckle interface and a cable extending between the cable end interface and the buckle assembly. The cable has a first end coupled to the cable end interface and an opposing second end coupled to the buckle assembly.
    Type: Application
    Filed: July 20, 2018
    Publication date: January 24, 2019
    Inventors: Andre Lee, Luis Cosio, David Durham, David Munn
  • Patent number: 10181027
    Abstract: Embodiments of an invention for an interface between a device and a secure processing environment are disclosed. In one embodiment, a system includes a processor, a device, and an interface plug-in. The processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to create a secure processing environment. The execution unit is to execute an application in the secure processing environment. The device is to execute a workload for the application. The interface plug-in is to provide an interface for the device to enter the secure processing environment to execute the workload.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Alpa Narendra Trivedi, Siddhartha Chhabra, Xiaozhu Kang, Prashant Dewan, Uday Savagaonkar, David Durham
  • Patent number: 10102370
    Abstract: Techniques to enable scalable cryptographically protected memory using on-chip memory are described. In one embodiment, an apparatus may comprise a processor component implemented on a first integrated circuit, an on-chip memory component implemented on the first integrated circuit, the on-chip memory component to include a memory page handler to manage memory pages stored on the on-chip memory component, and a cryptographic engine to encrypt and decrypt memory pages for the memory page handler, and an off-chip memory component implemented on a second integrated circuit coupled to the first integrated circuit, the off-chip memory component to store encrypted memory pages evicted from the on-chip memory component. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 16, 2018
    Assignee: INTEL CORPORATION
    Inventors: Alpa Narendra Trivedi, Siddhartha Chhabra, David Durham
  • Patent number: 10102380
    Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Francis X. McKeen, Carlos V. Rozas, Uday R. Savagaonkar, Simon P. Johnson, Vincent Scarlata, Michael A. Goldsmith, Ernie Brickell, Jiang Tao Li, Howard C. Herbert, Prashant Dewan, Stephen J. Tolopka, Gilbert Neiger, David Durham, Gary Graunke, Bernard Lint, Don A. Van Dyke, Joseph Cihula, Stalinselvaraj Jeyasingh, Stephen R. Van Doren, Dion Rodgers, John Garney, Asher Altman
  • Publication number: 20180279694
    Abstract: A base layer of a garment includes a waist section, an upper leg section, and a lower leg section. The waist section is positioned to correspond with and receive a waist and crotch region of a wearer. The waist section includes a base portion, a mesh portion, a compressive portion, and a durable portion. The upper leg section is positioned to correspond with and receive a thigh and knee region of the wearer. The upper leg section includes the base portion and the mesh portion. The lower leg section is positioned to correspond with and receive a shin and calf region of the wearer. The lower leg section includes the base portion and the compressive portion.
    Type: Application
    Filed: November 2, 2017
    Publication date: October 4, 2018
    Applicant: Fox Head, Inc.
    Inventors: Jake Theno, David Durham, Jillian Miranda, Tom Burgher, Lindsay Mellen
  • Publication number: 20180065051
    Abstract: There is provided a system for providing interactivity to a guest of an experiential venue, based on sensor measurement of the guest. The system comprises a sensor configured to sense a guest variable of the guest, where the sensor may be a biometric sensor, a facial recognition sensor, a voice stress analysis sensor, a gesture recognition sensor, a motion tracking sensor, or an eye tracking sensor, and may sense heart rate or another guest variable. The system also comprises a control system, which may be implemented as a computer, in communication with the sensor. The control system is configured to determine a guest state from the guest variable, and to modify a venue variable, for example by selecting a path a theme park ride follows. The control system modifies the venue variable according to the guest state to provide increased satisfaction to the guest of the experiential venue.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 8, 2018
    Inventors: David Crawford, David Durham, Jonathan Georges
  • Publication number: 20180047307
    Abstract: Various embodiments are generally directed an apparatus and method for processing an encrypted graphic with a decryption key associated with a depth order policy including a depth position of a display scene, generating a graphic from the encrypted graphic when the encrypted graphic is successfully decrypted using the decryption key and assigning the graphic to a plane at the depth position of the display scene when the encrypted graphic is successfully decrypted.
    Type: Application
    Filed: October 9, 2017
    Publication date: February 15, 2018
    Applicant: INTEL CORPORATION
    Inventors: Prashant Dewan, Uttam Sengupta, Uday R. Savagaonkar, Siddhartha Chhabra, David Durham, Xiaozhu Kang
  • Publication number: 20170372063
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for virtualization-based intra-block workload isolation. The system may include a virtual machine manager (VMM) module to create a secure virtualization environment or sandbox. The system may also include a processor block to load data into a first region of the sandbox and to generate a workload package based on the data. The workload package is stored in a second region of the sandbox. The system may further include an operational block to fetch and execute instructions from the workload package.
    Type: Application
    Filed: July 21, 2017
    Publication date: December 28, 2017
    Applicant: Intel Corporation
    Inventors: PRASHANT DEWAN, UTTAM SENGUPTA, SIDDHARTHA CHHABRA, DAVID DURHAM, XIAOZHU KANG, UDAY SAVAGAONKAR, ALPA NARENDRA TRIVEDI
  • Patent number: 9839856
    Abstract: There is provided a system for providing interactivity to a guest of an experiential venue, based on sensor measurement of the guest. The system comprises a sensor configured to sense a guest variable of the guest, where the sensor may be a biometric sensor, a facial recognition sensor, a voice stress analysis sensor, a gesture recognition sensor, a motion tracking sensor, or an eye tracking sensor, and may sense heart rate or another guest variable. The system also comprises a control system, which may be implemented as a computer, in communication with the sensor. The control system is configured to determine a guest state from the guest variable, and to modify a venue variable, for example by selecting a path a theme park ride follows. The control system modifies the venue variable according to the guest state to provide increased satisfaction to the guest of the experiential venue.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: December 12, 2017
    Assignee: Disney Enterprises, Inc.
    Inventors: David Crawford, David Durham, Jon Georges
  • Patent number: 9786205
    Abstract: Various embodiments are generally directed an apparatus and method for processing an encrypted graphic with a decryption key associated with a depth order policy including a depth position of a display scene, generating a graphic from the encrypted graphic when the encrypted graphic is successfully decrypted using the decryption key and assigning the graphic to a plane at the depth position of the display scene when the encrypted graphic is successfully decrypted.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: October 10, 2017
    Assignee: INTEL CORPORATION
    Inventors: Prashant Dewan, Uttam Sengupta, Uday R. Savagaonkar, Siddhartha Chhabra, David Durham, Xiaozhu Kang
  • Patent number: 9769123
    Abstract: One particular example implementation of an apparatus for mitigating unauthorized access to data traffic, comprises: an operating system stack to allocate unprotected kernel transfer buffers; a hypervisor to allocate protected memory data buffers, where data is to be stored in the protected memory data buffers before being copied to the unprotected kernel transfer buffers; and an encoder module to encrypt the data stored in the protected memory data buffers, where the unprotected kernel transfer buffers receive a copy the encrypted data.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Karanvir S. Grewal, Ravi L. Sahita, David Durham
  • Publication number: 20170185766
    Abstract: Various embodiments are generally directed to an apparatus, method, and other techniques to provide direct-memory access, memory-mapped input-output, and/or other memory transactions between devices designated for use by an enclave and the enclave itself. A secure device address map may be configured to map addresses for the enslave device and the enclave, and a register filter component may grant access to the enclave device to the enclave.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Inventors: ALPA NARENDRA TRIVEDI, RAVI SAHITA, DAVID DURHAM, KARANVIR GREWAL, PRASHANT DEWAN, SIDDHARTHA CHHABRA
  • Publication number: 20170177862
    Abstract: Techniques to enable scalable cryptographically protected memory using on-chip memory are described. In one embodiment, an apparatus may comprise a processor component implemented on a first integrated circuit, an on-chip memory component implemented on the first integrated circuit, the on-chip memory component to include a memory page handler to manage memory pages stored on the on-chip memory component, and a cryptographic engine to encrypt and decrypt memory pages for the memory page handler, and an off-chip memory component implemented on a second integrated circuit coupled to the first integrated circuit, the off-chip memory component to store encrypted memory pages evicted from the on-chip memory component. Other embodiments are described and claimed.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Inventors: ALPA NARENDRA TRIVEDI, SIDDHARTHA CHHABRA, DAVID DURHAM
  • Publication number: 20170109192
    Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.
    Type: Application
    Filed: December 27, 2016
    Publication date: April 20, 2017
    Inventors: Gilbert Neiger, Mayank Bomb, Manohar Castelino, Robert Chappell, David Durham, Barry Huntley, Anton Ivanov, Madhavan Parthasarathy, Scott Rodgers, Ravi Sahita, Vedvyas Shanbhogue
  • Patent number: 9563455
    Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: February 7, 2017
    Assignee: INTEL CORPORATION
    Inventors: Gilbert Neiger, Mayank Bomb, Manohar Castelino, Robert Chappell, David Durham, Barry Huntley, Anton Ivanov, Madhavan Parthasarathy, Scott Rodgers, Ravi Sahita, Vedvyas Shanbhogue
  • Patent number: 9335888
    Abstract: Systems and methods may provide for displaying a three-dimensional (3D) environment on a screen of a mobile device, and identifying a user interaction with an area behind the mobile device. In addition, the 3D environment can be modified based at least in part on the first user interaction. Moreover, the 3D environment may be modified based on movements of the mobile device as well as user interactions with the mobile device, allowing the user to navigate through the virtual 3D environment by moving the mobile/handheld device.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: May 10, 2016
    Assignee: Intel Corporation
    Inventors: Lenitra M. Durham, David Durham, Sangita Sharma