Abstract: The present invention relates to a pulse conditioning circuit including a first switch terminal having a first leg connected to a DC power source and a second leg. A second switch terminal is also provided having a first leg connected to an electrical ground and a second leg electrically connected to the second leg of the first switch. Pulses resulting from switch closures at the switch terminals are provided at the node where the second legs of both switch terminals are coupled. This node is preferably coupled to a low-pass filter, which is further coupled to a latch circuit providing a conditioned pulse output. The latch circuit is adapted to provide a first logic state output when the input of the latch is provided with a high logic state and a second logic state output when the input of the latch is provided with a low logic state. The high logic state input is provided when a switch connected to the first switch terminal is closed.

Abstract: Method and apparatus for testing the address/data paths between the ROM and CPU of a computer where the computer includes a first connector adapted to connect the ROM to the address/data paths so that data can be transferred between the CPU and the ROM via the data paths of the address/data paths and a second connector adapted to connect the CPU to the address/data paths so that addresses can be applied to an address decoder for the ROM via the address lines of the address/data paths. A memory is connected to the address decoder and the data lines via the first connector, the memory storing predetermined data at a plurality of memory locations. A kernel debugging module connected to the address/data paths via the second connector includes circuitry for successively applying read signals which emulate those provided by the CPU to successively read the predetermined data stored at the memory locations.