Abstract: A system for receiving and analyzing at least one inband user data packet within a CATV video signal. The system includes a data detector, a data processor and a memory. The data detector receives video signal samples of the data packet. The data detector includes a data slicer used to determine a threshold level based on a clock sync byte located in the data packet. The threshold level is compared to subsequent video signal samples of the data packet. The data processor determines the destination of the data packet. The memory selectively stores the data packet until it is required by the data processor.

Abstract: A system for synchronizing one or more decoders with a network sync signal at a headend of a television communication network. The system allows decoders to transmit upstream messages synchronously in time slots which are defined according to the network sync signal, thereby improving system throughput. Identifying data is provided in a blanking interval (VBI or HBI) of one or more television signals to designate a horizontal scan line of the respective television signal which follows a reference point in the network sync signal by a predetermined delay. At each decoder, the identifying data is recovered, and the onset of the designated scan line can be used to signal the start of a transmission for the decoder. Preferably, the identifying data is provided in each television signal so the user is not forced to tune to a particular television channel to transmit a message. Various channel access protocols may be used, such as a session oriented protocol, or a synchronized ALOHA protocol.

Abstract: A plurality of synchronized phase generators are provided in a mainframe computer of the type having unit card each of which contain a plurality of very large scale integrated (VLSI) logic chips. Each logic chip has its own on-chip phase generator which is controlled by off-chip control signals. The on-chip phase generations each comprise output phase control gates coupled to: an on-chip start shift register, a stop shift register, clock shift registers which provide the phase of the clock, and start-stop run controls all of which are coupled to off-chip control signals and to the output phase control gates which are synchronized to eliminate distortion and skew between phase generators on different logic chips.