Abstract: A package for a medical device such as an intermittent catheter has a case and a cap connected by threads. The case includes a hollow tube which is closed at one end and open at the other. A shoulder is formed near one end of the case. Above the shoulder is a cylindrical ferrule that includes external threads. The cap has internal threads selectably engageable with the threads on the ferrule to form a liquid-tight seal between the cap and case when the cap is installed on the case.

Abstract: In some embodiments, the present disclosure relates to a system. The system includes a substrate and a fluid capture material formed on one or more surfaces of the substrate. The fluid capture material includes a sorbent material that binds one or more fluids, the one or more fluids comprising water, carbon dioxide, sulfur oxides, or a combination thereof. The fluid capture material also includes one or more binder materials, wherein the binder material is at least partially cross-linked.

Abstract: A low cost, low phase noise microwave synthesizer includes a DDS modulation circuit and a phase-locked loop. The DDS modulation circuit modulates the output of a DDS to a high frequency. The phase-locked loop downconverts the DDS output and locks the downconverted signal to a relatively low frequency, fixed reference.

Abstract: A low cost, low phase noise microwave synthesizer includes a DDS modulation circuit and a phase-locked loop. The DDS modulation circuit modulates the output of a DDS to a high frequency. The phase-locked loop downconverts the DDS output and locks the downconverted signal to a relatively low frequency, fixed reference.

Abstract: A timing circuit for ATE generates an output clock from an input clock and controls output pulse width. The timing circuit includes a differential driver having an input that receives the input clock, and having inverting and non-inverting outputs. The inverting output is coupled to a first phase-locked loop, and the non-inverting output is coupled to a second phase-locked loop. The first and second phase-locked loops respectively generate first and second clocks in response to respective rising and falling edges of the input clock. A combiner circuit converts the first and second clocks into narrow pulse trains, and the pulse trains respectively operate SET and RESET inputs of a SET/RESET flip-flop. The SET/RESET flip-flop generates an output clock having rising edges responsive to rising edges of the input clock, and falling edges responsive to falling edges of the input clock.