Patents by Inventor David Edward Kotecki
David Edward Kotecki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6727174Abstract: The present invention discloses a multi-diameter electrical conductor for use as an embedded plug in a microelectronic device. The multi-diameter electrical conductor consists of a body portion which has a first diameter, and at least one neck portion in contact with the body portion that has at least a second diameter smaller than the first diameter. In a preferred embodiment, the multi-diameter conductor is a dual-diameter conductor providing electrical communication between an electrode and an active circuit element in a semiconductor structure and comprising a lower body portion and an upper neck portion. The conductive materials used in forming the body portion and the neck portion of the contact plug can be selected from doped polysilicon, refractory metals, metal silicides, low resistivity metals, noble metals and their alloys, adhesion layers, metallic diffusion barrier layers, and oxide and nitride diffusion barrier materials.Type: GrantFiled: August 22, 2000Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: David Edward Kotecki, Katherine Lynn Saenger
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Patent number: 6420272Abstract: In semiconductor dynamic random access memory circuits using stacked capacitor storage elements formed using high permittivity dielectric material, it is typical to form the stacked capacitors using noble metal electrodes. Typically, the etching process for the noble metal electrodes requires the use of a hard mask patterning material such as silicon oxide. Removal of this hard mask frequently results in damage to the dielectric surface surrounding the patterned noble metal electrode.Type: GrantFiled: December 14, 1999Date of Patent: July 16, 2002Assignees: Infineon Technologies A G, International Business Machines CorporationInventors: Hua Shen, David Edward Kotecki, Satish D. Athavale, Jenny Lian, Gerhard Kunkel, Nimal Chaudhary
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Patent number: 6323127Abstract: A noble metal electrode structure having a cup-like, approximately cylindrical shape, roughened inner and outer surfaces, and a surface area of at least 1 sq. micron or greater is provided as well as a capacitor which includes the noble metal electrode as a bottom electrode. The high-surface area noble metal electrode is formed by electroplating into annular channels that have roughened sidewalls formed by the oxidation of vapor-deposited Si nuclei.Type: GrantFiled: June 22, 2000Date of Patent: November 27, 2001Assignee: International Business Machines CorporationInventors: Panayotis Andricacos, Gregory Costrini, David Edward Kotecki, Katherine Lynn Saenger
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Patent number: 6242321Abstract: Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.Type: GrantFiled: May 3, 1999Date of Patent: June 5, 2001Assignee: International Business Machines CorporationInventors: Raul Edmundo Acosta, James Hartfiel Comfort, Alfred Grill, David Edward Kotecki, Katherine Lynn Saenger
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Patent number: 6136664Abstract: A method of forming a trench isolation on a semiconductor substrate comprising the steps of forming a trench in the substrate, partially filling the trench with a first layer of polysilicon, oxidizing the first layer of polysilicon, partially filling the trench with at least a second layer of polysilicon, and oxidizing the second layer of polysilicon. By utilizing the method of the present invention, formation of voids and defects in a trench isolation having a high aspect ratio can be prevented.Type: GrantFiled: August 7, 1997Date of Patent: October 24, 2000Assignee: International Business Machines CorporationInventors: Laertis Economikos, David Edward Kotecki, Jack A. Mandelman
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Patent number: 6131258Abstract: A capacitor structure with a generally L-shaped non-conductor having a horizontal portion and a vertical portion, the vertical portion defining a first opening formed therein; a generally U-shaped conductor formed within the first opening; and a generally L-shaped conductor formed exterior to the generally L-shaped non-conductor.Type: GrantFiled: August 7, 1997Date of Patent: October 17, 2000Assignee: International Business Machines CorporationInventors: Katherine Lynn Saenger, James H. Comfort, Alfred Grill, David Edward Kotecki
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Patent number: 6027966Abstract: A capacitor structure is provided, with a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening.Type: GrantFiled: August 13, 1997Date of Patent: February 22, 2000Assignee: International Business Machines CorporationInventors: Katherine Lynn Saenger, James H. Comfort, Alfred Grill, David Edward Kotecki
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Patent number: 6015985Abstract: The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.Type: GrantFiled: June 17, 1997Date of Patent: January 18, 2000Assignee: International Business Machines CorporationInventors: Herbert Lei Ho, David Edward Kotecki, Carl John Radens
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Patent number: 5998250Abstract: This invention is directed to a semiconductor memory device including a storage element comprising a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.Type: GrantFiled: April 17, 1998Date of Patent: December 7, 1999Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, David Edward Kotecki, Katherine Lynn Saenger
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Patent number: 5932907Abstract: A layered structure is described incorporating a noble metal silicide, a noble metal and an oxygen-rich barrier layer between the noble metal silicide and noble metal. A silicon-contributing substrate may also be present in addition to or without the noble metal silicide. The invention overcomes a problem in fabricating capacitors containing high-epsilon dielectric materials or ferroelectric memory elements containing ferroelectric material, namely that silicon diffuses through the electrode in one direction and oxygen diffuses through the electrode in the other direction during the high temperature (400-700.degree. C.) deposition and processing of the dielectric.Type: GrantFiled: May 30, 1997Date of Patent: August 3, 1999Assignee: International Business Machines CorporationInventors: Alfred Grill, David Edward Kotecki, Katherine Lynn Saenger
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Patent number: 5914851Abstract: A capacitor structure is provided, with a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening.Type: GrantFiled: December 22, 1995Date of Patent: June 22, 1999Assignee: International Business Machines CorporationInventors: Katherine Lynn Saenger, James H. Comfort, Alfred Grill, David Edward Kotecki
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Patent number: 5849638Abstract: The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.Type: GrantFiled: January 21, 1997Date of Patent: December 15, 1998Assignee: International Business Machines CorporationInventors: Herbert Lei Ho, David Edward Kotecki, Carl John Radens
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Patent number: 5825609Abstract: This invention is directed to a semiconductor memory device including a storage element having a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.Type: GrantFiled: April 23, 1996Date of Patent: October 20, 1998Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, David Edward Kotecki, Katherine Lynn Saenger
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Patent number: 5789320Abstract: Noble metal plating on a preexisting seed layer is used in the fabrication of electrodes for DRAM and FRAM. The plating may be spatially selective or nonselective. In the nonselective case, a blanket film is first plated and then patterned after deposition by spatially selective material removal. In the selective case, the plated deposits are either selectively grown in lithographically defined areas by a through-mask plating technique, or selectively grown as a conformal coating on the exposed regions of a preexisting electrode structure. A diamond-like carbon mask can be used in the plating process. A self-aligned process is disclosed for selectively coating insulators in a through-mask process.Type: GrantFiled: April 23, 1996Date of Patent: August 4, 1998Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, James Hartfiel Comfort, Alfred Grill, David Edward Kotecki, Vishnubhai Vitthalbhai Patel, Katherine Lynn Saenger, Alejandro Gabriel Schrott
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Patent number: 5757612Abstract: Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.Type: GrantFiled: April 23, 1996Date of Patent: May 26, 1998Assignee: International Business Machines CorporationInventors: Raul Edmundo Acosta, James Hartfiel Comfort, Alfred Grill, David Edward Kotecki, Katherine Lynn Saenger
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Patent number: 5712759Abstract: A capacitor structure with a generally L-shaped non-conductor having a horizontal portion and a vertical portion, the vertical portion defining a first opening formed therein; a generally U-shaped conductor formed within the first opening; and a generally L-shaped conductor formed exterior to the generally L-shaped non-conductor.Type: GrantFiled: December 22, 1995Date of Patent: January 27, 1998Assignee: International Business Machines CorporationInventors: Katherine Lynn Saenger, James H. Comfort, Alfred Grill, David Edward Kotecki
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Patent number: 5701647Abstract: A capacitor structure is provided, with a first conductor on top of a substrate having at least one layer of dielectric material thereon; a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein; a second conductor, in electrical contact with the first conductor, formed on the sidewalls of the first opening; a non-conductive sidewall spacer formed in the first opening and contacting the second conductor, the non-conductive sidewall spacer having a second opening formed therein; and a third conductor formed in the second opening.Type: GrantFiled: January 22, 1997Date of Patent: December 30, 1997Assignee: International Business Machines CorporationInventors: Katherine Lynn Saenger, David Edward Kotecki
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Patent number: 5675471Abstract: An electrostatic chuck (ESC) provides increased temperature uniformity and adjustment capability of the surface of a wafer or wafer-like workpiece during processing, for example, in an electron-cyclotron-resonance chemical vapor deposition (ECR-CVD) reactor. Temperature uniformity is achieved through an improved pattern of grooves in the face of the ESC which allows an inert gas to be contained between the ESC and a wafer held thereby even at high levels of vacuum. The ESC is adapted for a particular desired temperature range by choice of surface roughness of the remaining areas of the face of the ESC. Adjustability within that range is achieved by variation of the electrostatic voltage by which a wafer is held against the chuck face. Increased surface roughness and/or decreased contact area fraction may be used to achieve high wafer temperatures.Type: GrantFiled: June 7, 1995Date of Patent: October 7, 1997Assignee: International Business Machines CorporationInventor: David Edward Kotecki