Patents by Inventor David Edward McCracken
David Edward McCracken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8447910Abstract: This disclosure involves methods and systems for providing a host with a Bluetooth transceiver by way of a virtual USB connection to a PCI/PCIe bus in which the virtual USB connection is controlled by a modified OHCI. The Bluetooth transceiver is configured to send a status signal when there is data to be transferred to the host. The modified OHCI is configured to activate a list processor upon receipt of the status signal, such that the list processor controls the transfer of the data to be transferred to the host. After delivery of the data to the host, the modified OHCI is configured to inactivate the list processor. Further, the modified OHCI is configured to be compatible with standard USB software resident on the host.Type: GrantFiled: November 30, 2010Date of Patent: May 21, 2013Assignee: QUALCOMM IncorporatedInventors: Seung Baek Yi, David Edward McCracken
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Patent number: 7881321Abstract: A multiprocessor computer system includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each node controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port is connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. The memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips.Type: GrantFiled: July 28, 2008Date of Patent: February 1, 2011Assignee: Silicon Graphics InternationalInventors: Martin M. Deneroff, Givargis G. Kaldani, Yuval Koren, David Edward McCracken, Swaminatham Venkataraman
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Publication number: 20090024833Abstract: Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip.Type: ApplicationFiled: July 28, 2008Publication date: January 22, 2009Applicant: Silicon Graphics, Inc.Inventors: Martin M. Deneroff, Givargis G. Kaldani, Yuval Koren, David Edward McCracken, Swaminathan Venkataraman
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Patent number: 7406086Abstract: Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip.Type: GrantFiled: June 15, 2004Date of Patent: July 29, 2008Assignee: Silicon Graphics, Inc.Inventors: Martin M. Deneroff, Givargis G. Kaldani, Yuval Koren, David Edward McCracken, Swami Venkataraman
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Patent number: 6751698Abstract: Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip.Type: GrantFiled: September 29, 1999Date of Patent: June 15, 2004Assignee: Silicon Graphics, Inc.Inventors: Martin M. Deneroff, Givargis G. Kaldani, Yuval Koren, David Edward McCracken, Swami Venkataraman
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Patent number: 6453408Abstract: A method for controlling memory page migration in a parallel processor computer (10) is provided that comprises requesting access to a memory page (14) by a requester processor (206). The method then determines whether the requester processor (206) is a local processor or a remote processor. The method then increments a local access counter (52) and identifies the local access counter (52) as an incremented counter in response to determining that the requester processor (206) is a local processor. If the requester processor (206) is determined to be a remote processor, the method increments a remote access counter (54) and identifies the remote access counter (54) as the incremented counter. The method next sets a threshold processing indicator to a positive value if the incremented counter exceeds a value threshold (58) or if a difference between the local access counter (52) and the remote access counter (54) exceeds a difference threshold (62).Type: GrantFiled: September 30, 1999Date of Patent: September 17, 2002Assignee: Silicon Graphics, Inc.Inventors: James A. Stuart Fiske, David Edward McCracken, Leonard Mark Widra
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Patent number: 6215686Abstract: A memory system that includes switches for controlling data transfer that are disposed on the motherboard. The switches are selectively coupled to a controller and to connector receptacles that are adapted to receive a memory module. The memory system also includes resistors that are disposed on the motherboard for terminating data signals. In one embodiment, memory modules are accessed in pairs. That is, the data switches are used to control the flow of data signals such that data signals only flow to one pair of memory modules at any particular time. In one embodiment, the memory system of the present invention includes eight memory modules that use DDR SDRAM memory components. When 8 Mbit, 16 Mbit, 32 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 128 megabytes (Mbytes) to 1 gigabyte (Gbyte).Type: GrantFiled: August 27, 1999Date of Patent: April 10, 2001Assignee: Silicon Graphics, Inc.Inventors: Martin M. Deneroff, Kenneth M. Sarocky, David Leo McCall, David Edward McCracken
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Patent number: 6115278Abstract: A memory system that includes switches for controlling data transfer that are disposed on the motherboard. The switches are selectively coupled to a controller and to connector receptacles that are adapted to receive a memory module. The memory system also includes resistors that are disposed on the motherboard for terminating data signals. In one embodiment, memory modules are accessed in pairs. That is, the data switches are used to control the flow of data signals such that data signals only flow to one pair of memory modules at any particular time. In one embodiment, the memory system of the present invention includes eight memory modules that use DDR SDRAM memory components. When 8 Mbit, 16 Mbit, 32 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 128 megabytes (Mbytes) to 1 gigabyte (Gbyte).Type: GrantFiled: February 9, 1999Date of Patent: September 5, 2000Assignee: Silicon Graphics, Inc.Inventors: Martin M. Deneroff, Kenneth M. Sarocky, David Leo McCall, David Edward McCracken