Abstract: A novel semiconductor memory having a plurality of storage devices arranged in and X-Y array wherein the Input and Output data lines of the array are routed over a portion of the memory array. The Input and Output data lines are routed symmetrically between and in parallel with the small-signal bit-line pairs of the array which access the individual storage devices. The individual bit-lines of a bit-line pair cross-over one another at the midpoint of the portion of the array over which the Input and Output lines am routed. Buffers are included on the Input and Output lines at the periphery of the array in order to prevent noise external to the array from being transmitted into the array on the I/O data lines above the array. Output buffers are also provided to drive output data out across the array. Additionally, circuitry is provided for preventing the Input and Output lines from transitioning while small-signals are being developed on the bit-line pairs.

Abstract: An apparatus is described for re-configuring a partial product reduction tree. The partial product reduction tree contains carry-save-adders and is represented by a plurality of rectangles and triangles, wherein each rectangle has a corresponding triangle such that a rectangle-triangle pair is formed for each rectangle. The apparatus includes a plurality of switches located between a corresponding plurality of the rectangle-triangle pairs such that each switch has an adjacent rectangle and an adjacent triangle. A first signal line extends from each switch to the switch's adjacent rectangle, a second signal line extends from each switch to the switch's adjacent triangle, and a third signal line extends from each switch to the rectangle of the rectangle-triangle pair which is adjacent to the switch.