Abstract: Systems and methods according to the present invention provide serial communication devices which are pin-configurable at power on to operate as either a root (20) or endpoint (22) device. In conjunction with, for example, PCI Express specified I/O data buses (24), such devices provide for efficient transfer of serial data between systems and devices.

Abstract: Systems and methods according to the present invention provide serial communication devices which are pin-configurable at power on to operate as either a root (20) or endpoint (22) device. In conjunction with, for example, PCI Express specified I/O data buses (24), such devices provide for efficient transfer of serial data between systems and devices.

Abstract: Described is a data communication arrangement (100) with a transmit module adapted to convert parallel data words (102) into a plurality of serial data streams (122, 124, 126, 128), the transmit module arranged in a plurality of groups, with each group including a data-carrying line (122, 124, 126, 128). A receive module (200) is adapted to collect the digital data carried from the transmit module (100) over the plurality of data-carrying lines (122, 124, 126, 128). The receive module (200) detects a frequency compensation code, and in response provides a code-detected signal used for aligning the data back into parallel words and mitigating skew-caused re-training and configuration sequences. The receive module (200) may continuously check alignment between the groups and autonomously correct alignment of the plurality of data groups.

Abstract: A data processing system, circuit arrangement, and method to communicate data over a multi-channel serial communications interface (14) using a dedicated encrypted virtual channel from among multiple virtual channels supported by the communications interface (14). Encryption for the dedicated encrypted virtual channel is provided by a hardware encryption circuit (34) that is coupled to the interface, such that encryption may be performed at a relatively low level, and with substantial protection from compromise, particularly along chip boundaries. In one particular application, access control may be provided for a digital data stream using a multi-chip access control scheme that relies on one chip (148) to provide access control over a received digital data stream, with another chip (150) utilized to process the digital data stram once authorized to do so.

Abstract: A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

Abstract: An improved memory addressing system has a CPU having both an address bus and a multiplexed data/address bus. A reduced PIN out companion chip is coupled to the multiplexed data/address bus for decoding data and low order address information. Memory storage is coupled to a high order address bus for receiving a high order address from the CPU, and to the low order address bus and data bus for receiving decoded low order address and data information from the companion chip.

Abstract: A system and method for accelerating information transfers from an encrypted memory to a requesting device in a system utilizing a decryption engine is provided. The decryption engine fetches and decrypts a first information block having a greater byte count than the number of bytes of requested information. A current address, corresponding to a storage device address of the decrypted first information block residing at the output of the decryption engine, is compared to a requested address. The requested address corresponds to a storage device address of a second information block of which the requested information is a subset thereof. The second information block has a byte count equivalent to the byte count of the first information block which was decrypted by the decryption engine. A new block fetch of encrypted information from the encrypted storage device is initiated when the current address and the requested address are unequal.

Abstract: An endian domain conversion circuit for converting data packets transmitted between two bus interfaces. The novel system advantageously eliminates any requirement for a large bit switch within the circuit's write data path. Instead, endian conversion intelligence is placed into the read data path. Double words (dwords) are individually received from an incoming data packet and bytes are parallel stored into the same byte location of several different first-in-first-out (FIFO) memories. In one example, the dwords are 32-bits each and the number FIFO memories used is four. An entire input data packet is received in this manner, incrementing the write address of the FIFO memories for each dword. Depending on the type of endian domain conversion required, if at all, endian conversion control circuitry of the present invention controls the manner in which the four exemplary FIFO memories are read (via a read pointer) and the manner which their data is supplied over the output bus to generate the output data.

Abstract: A portable computer and corresponding docking station, where the portable computer may be inserted into or removed from the docking station without concern relating to the state of either the portable computer or of the docking station. The hot docking sequence is performed by establishing a direct connection to the primary PCI bus without the risk of any possible system damage, file damage, or data loss. This can be accomplished even while the portable computer system is powered on and is actively running. The present invention prevents glitches from occurring in pre-existing pins and adds four new pins to implement this novel hot docking sequence. Furthermore, hot undocking can be readily performed as well by basically reversing the docking sequence.