Abstract: A method and system are disclosed for: (a) matching a machine-implemented process simulator with an actual fabrication line, (b) using the matched model to simulate the statistical results of mass production by the modeled production line, (c) using the model to predict cross-reticle variance from collected data for in-scribe features, (d) using the model to decompose the variance contributions of each process parameter and identify the more prominent contributors, and (e) using the model to identify the process parameter adjustments which would provide best leverage when taken one at a time.

Abstract: A method and system are disclosed for: (a) matching a machine-implemented process simulator with an actual fabrication line, (b) using the matched model to simulate the statistical results of mass production by the modeled production line, (c) using the model to predict cross-reticle variance from collected data for in-scribe features, (d) using the model to decompose the variance contributions of each process parameter and identify the more prominent contributors, and (e) using the model to identify the process parameter adjustments which would provide best leverage when taken one at a time.

Abstract: Metal pillars (18) having diameters of less than about 1.0 .mu.m are grown in vias (16) in dielectric layers (14) between metal layers (12, 22) by a process comprising: (a) forming a first metal layer (12) at a first temperature and patterning the metal layer; (b) forming the dielectric layer to encapsulate the first patterned metal layer, the dielectric layer having a compressive stress of at least about 100 MegaPascal and being formed at a second temperature; (c) opening vias in the dielectric layer to exposed underlying portions of the patterned metal layer, the vias being less than about 1.0 .mu.m in diameter; (d) heating the semiconductor wafer at a temperature that is greater than either the first or second temperatures to induce growth of metal in the vias from the metal layer; and (e) forming the second metal layer (22) over the dielectric layer to make contact with the metal pillars.

Abstract: Metal pillars (18) having diameters of less than about 1.0 .mu.m are grown in vias (16) in dielectric layers (14) between metal layers (12, 22) by a process comprising: (a) forming a first metal layer (12) at a first temperature and patterning the metal layer; (b) forming the dielectric layer to encapsulate the first patterned metal layer, the dielectric layer having a compressive stress of at least about 100 MegaPascal and being formed at a second temperature; (c) opening vias in the dielectric layer to exposed underlying portions of the patterned metal layer, the vias being less than about 1.0 .mu.m in diameter; (d) heating the semiconductor wafer at a temperature that is greater than either the first or second temperatures to induce growth of metal in the vias from the metal layer; and (e) forming the second metal layer (22) over the dielectric layer to make contact with the metal pillars.