Abstract: A programmable multiple current source includes a plurality of current source circuits each having current level data storage circuitry. A current level data input terminal and a control input terminal are connected to each current source circuit to supply current level data to the storage circuitry. Peak detector and storage circuitry is coupled to each of the output terminals of the current source circuits. Each associated current source circuit includes a master digital-to-analog converter coupled to the current level data storage circuitry, a driver circuit coupled to the digital-to-analog converter and to the associated current source circuit, comparator and storage circuitry having a first input coupled to the peak detector and storage circuitry and a second input coupled to the driver circuit, and current level adjustment circuitry coupled to the comparator and storage circuitry and the driver circuit.

Abstract: A memory circuit (24) limits the threshold voltage distribution for either programming or erasing a memory cell (40A) in a non-volatile memory array (34). A data latch (90) provides a current (I.sub.REF) to the memory cell (40A) that increases in current as the operating temperature of the memory cells (40A, 40B) increases. Current generated by the data latch (90) increases when the processing parameters cause a greater conductivity of the transistors in the memory cell (40A) and the current decreases when the processing parameters cause a lesser conductivity of the transistors in the memory cell (40A), thus allowing narrower limits on the distribution of the program and erase threshold voltages.

Abstract: A circuit (28) and method of sensing data stored in a memory circuit provide a reference current (I.sub.REF) that tracks memory cell current (I.sub.BIT) over a range of temperatures and power supply voltages. A comparator circuit (66) senses the memory cell current with respect to the reference current to produce the stored data (V.sub.DATA) By sensing current rather than voltage, the voltage swing on a high capacitance bitline (39) can be reduced to improve speed. The reference current is set during testing of the circuit by applying programming voltages (V.sub.WELL, V.sub.CG, V.sub.BL) to a reference device (52) that matches a storage device (36) in the memory cell (30).

Abstract: A current limiting circuit (70) controls the leakage current of a memory circuit (24) of a portable wireless device (10) while operating in a standby mode. A first semiconductor well (64) isolates the memory circuit (24) that is disposed in a second semiconductor well (66) from a substrate (62). In the standby mode the current limiting circuit (70) is switched to a non-conduction mode that limits the leakage currents of a diode formed by the first semiconductor well (66) with the second semiconductor well (64) and a diode formed by the second semiconductor well (64) with the substrate (62).

Abstract: A memory circuit (24) includes a sense amp circuit (30) that uses multiplexers (86) in a column mux (32) for pre-charging only selected bitlines in order to limit the current during a read operation of the FLASH memory circuit (24). The sense amp circuit (30) provides the bitline with a pre-charge voltage that is set by a current reference (68) that is substantially supply independent. In the read mode the sense amp circuit (30) responds to either a voltage on the bitline that is lowered from the pre-charge voltage value by a selected programmed memory cell (40) or by a voltage that remains at the pre-charged voltage value for an unprogrammed memory cell.

Abstract: A method for generating a programmable bandgap output reference voltage (V.sub.REF31) and a voltage reference circuit (31) have been provided. The voltage reference circuit (31) includes a pair of bipolar transistors (33, 34), a resistor (36), an operational amplifier (32) and a plurality of field effect transistors (38, 39, 41) configured to generate a current (I.sub.1 ') having a positive temperature coefficient. In addition, the voltage reference circuit (31) includes a resistor (46), an operational amplifier (44), another plurality of field effect transistors (47, 48) which, in conjunction with one (34) of the pair of bipolar transistors, generates a current (I.sub.2 ') having a negative temperature coefficient. The current (I.sub.1 ') having the positive temperature coefficient is summed with the current (I.sub.2 ') having the negative temperature coefficient to form a current having a zero temperature coefficient, which is used to develop a voltage having a zero temperature coefficient.

Abstract: An Input/Output (I/O) circuit (11) for an integrated circuit including Electrostatic Discharge Protection (ESD) circuitry is disclosed. A Silicon Controlled Rectifier SCR (30) is triggered by a transistor (36) which is scaled to an output transistor (24) of the I/O circuit (11) to shunt an ESD event. The SCR (30) couples between a pad (12) and a power supply line V.sub.SS. The transistor (36) is disabled. The triggering mechanism is voltage breakdown of the transistor (36) due to an ESD event. The SCR protection mechanism is process independent since the triggering mechanism is formed similarly to the output transistor (24) and thus breaks-down similarly. Zener diodes (26-29) are coupled to gates of the I/O circuit (11) and between the power supply lines. A phosphorous doping less than 5.0 E18 per cubic centimeter is used to form the cathode of zener diodes (26-29).

Abstract: A voltage driven control die (20) for use with a power device (22) has been provided. The voltage driven control die includes an under voltage lock-out circuit (46) which inhibits drive to the power device until the input voltage exceeds a predetermined threshold voltage. Moreover, the control die includes a noise immunity enhancement circuit (56) for providing an excess reverse bias across an output SCR (58) for preventing false triggering of the output SCR. The control die also includes circuitry (40, 44) for detecting an over temperature or an over current condition within the power device.

Abstract: A multi-leaded protected power device having a boot-strap input has been provided. The power device includes a current controlled, boot-strap driven control die (20) for use with a power transistor (25). The control die includes an under voltage lock-out circuit (46) which inhibits drive to the power transistor until the input signals exceed a predetermined threshold level. Moreover, the control die includes a noise immunity enhancement circuit (56) for providing an excess reverse bias across an output SCR (58) for preventing false triggering of the output SCR. The power device further includes a status output lead (204) for indicating when a voltage occurring across the power transistor has exceeded a predetermined threshold, and a current output lead (220) for providing a current that is proportional to a current flowing through the power transistor.

Abstract: A micromachined capacitor structure having a first anchor (12) attached to the substrate (24), a tether (13) coupled to the anchor (12) and having a portion free to move in a lateral direction over the substrate (24) in response to acceleration. A tie-bar (14) is coupled to the movable portion of the tether (13), and at least one movable capacitor plate (16) is coupled to the tie bar (13). A first fixed capacitor plate (16) is attached to the substrate (24) laterally overlapping and vertically spaced from the at least one movable capacitor plate (16).

Abstract: A detection circuit for sensing small capacitive changes has been provided. The detection circuit includes a dummy integrator stage that compensates for a voltage step that results from charge injection due to an existing switch in a first integrator stage. As a result, the detection circuit is insensitive to switch injection and amplifier offset voltages.

Abstract: A semiconductor device having a power switch (12) and a saturation detection diode (13) formed in an upper surface of a semiconductor drift region (11) is provided. The saturation detector diode (13) and the power switch (12) are electrically coupled by the drift region (11). An external signal applied to the detector diode (13) forward biases the detector diode (13) when the drift region (11) potential is below a predetermined voltage and the detector diode (13) becomes reverse biased when the drift region (11) potential is greater than the predetermined voltage.

Abstract: A control circuit for protecting a power device has been provided. The control circuit has a thermal shutdown circuit for activating a first SCR when the temperature of the control circuit exceeds a predetermined temperature. Additionally, the control circuit has a DSAT detection circuit for activating the first SCR in response to an external signal. The first SCR is coupled across an input terminal and the common terminal of the control circuit. When the first SCR latches, it functions to subsequently latch a second SCR that is coupled across the output and common terminals. The second SCR functions to rapidly discharge the voltage appearing across the output and common terminals.Additionally, the control circuit includes an input level sensitive circuit which may be utilized to deactivate various circuitry depending upon the current level of an input signal supplied to the control circuit.

Abstract: A memory circuit which includes a memory SCR and an output SCR is provided. The memory SCR is coupled between the input terminal and the common terminal of the memory circuit wherein the input terminal is the control terminal of the output SCR and the output SCR is coupled across the output terminal and the common terminal of the memory circuit. When the memory SCR latches, it functions to subsequently latch the output SCR. Because the output SCR has a greater forward operating voltage than the memory SCR and by providing a current path from the output terminal to the memory SCR, the memory SCR remains latched during the transition period of when the output SCR goes from a latched state to an unlatched state.

Abstract: A current source with adjustable temperature compensation in which the level of current supplied to a load is adjusted to compensate for the load's inherent change in performance with changes in temperature. The current source allows selection of the appropriate temperature compensating characteristic and operating current solely by altering internal component values.

Abstract: A method for protecting a semiconductor power die has been provided. The method involves inserting an integrated circuit die between the gate lead of a package containing the semiconductor power die and the actual gate terminal of the semiconductor power die. As a result, any current flowing into the gate lead of the package must pass through the integrated circuit die before entering the semiconductor power die. This allows the integrated circuit die to monitor and control the semiconductor power die.

Abstract: A voltage reference circuit is provided for developing an output voltage operating independent of temperature and power supply variation. A current reference circit provides a current reference signal operating independent of power supply variation and having a predetermined temperature coefficient and flowing through a first transistor and a first resistor each having opposite temperature coefficients. The output voltage is established as the sum of the base-emitter junction potential of the first transistor and the potential developed across the first resistor. The temperature coefficient of the potential developed across the first resistor substantially cancels the temperature coefficient across the base-emitter junction of the first transistor thereby providing the output voltage operating independent of temperature and power supply variation.

Abstract: An integrated circuit digital-to-analog converter includes a nichrome feedback resistor having .+-.1% accuracy in its output amplifier, a plurality of bit current determining resistors that have .+-.30% manufacturing accuracy, a bias voltage circuit that produces a temperature-compensated bias voltage including an integrated potentiometer that is laser trimmed to compensate for the inaccuracy of the bit current determining resistors. The bit current determining resistors thereby produce constant, precise temperature-independent bit currents. The integrated potentiometer is accurately laser trimmed without changing the series resistance of the potentiometer. This prevents current density changes that change the temperature sensitivity of temperature-compensating elements in the bias voltage circuit.

Abstract: A low voltage sixteen bit digital-to-analog converter operable between +5 and -5 volt power supplies and capable of providing output voltage levels to within about 1.4 volts of +V.sub.CC and -V.sub.CC includes a push-pull output stage with only a pullup transistor and a pulldown transistor connected in series between the positive and negative supply voltages. The output stage includes circuitry that reduces the base voltage of the pullup transistor or pulldown transistor enough to reduce its collector current to near zero, greatly increasing its effective collector-to-emitter breakdown voltage.