Abstract: The first-in/first-out (FIFO) buffer includes a first bank of individual storage elements for storing even data and a second bank of individual storage locations for storing odd data. Precharge elements are provided for precharging the even array while data is read from the odd array during one clock cycle and for precharging the odd array while data is read from the even array during a next subsequent clock cycle. Hence, only half of the array is precharged during any one clock cycle. The FIFO buffer is driven by a clock signal having a clock period equal to a minimum precharge time. A 3-input multiplexer is provided with 3 inputs connected, respectively, to an output line of the even array, an output line of the odd array, and an overall input line. In circumstances where data needs to be written to and read from the same storage element in one clock cycle, the multiplexer selects the input line thereby allowing the input data to bypass the storage array for immediate output.