Patents by Inventor David Fraser Rae
David Fraser Rae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11670599Abstract: Packages are configured to include an electromagnetic interference (EMI) shield. According to one example, a package includes a substrate, an electrical component, and an EMI shield. The substrate includes a first surface and a second surface. The electrical component may be coupled to the first side of the substrate. The EMI shield is formed with at least one passive device. The at least one passive device is coupled to the first surface of the substrate. The at least one passive device is located laterally to the at least one electrical component, and extends along at least a portion of the electrical component. Other aspects, embodiments, and features are also included.Type: GrantFiled: July 9, 2020Date of Patent: June 6, 2023Assignee: QUALCOMM INCORPORATEDInventors: Jeahyeong Han, David Fraser Rae, Rajneesh Kumar
-
Patent number: 11502049Abstract: A package that includes a first redistribution portion, a second redistribution portion, a third redistribution portion, a first encapsulation layer coupled to the first redistribution portion and the third redistribution portion, a first discrete device encapsulated by the first encapsulation layer, wherein the first discrete device is located between the first redistribution portion and the third redistribution portion, a second encapsulation layer coupled to the first redistribution portion and the second redistribution portion, and a second discrete device encapsulated by the second encapsulation layer, wherein the second discrete device is located between the first redistribution portion and the second redistribution portion.Type: GrantFiled: May 6, 2020Date of Patent: November 15, 2022Assignee: QUALCOMM IncorporatedInventors: Aniket Patil, David Fraser Rae, Hong Bok We
-
Patent number: 11404343Abstract: A package that includes a first substrate, an integrated device coupled to the first substrate, a second substrate coupled to the integrated device, and an encapsulation layer located between the first substrate and the second substrate. The second substrate is configured to operate as a heat spreader. The second substrate is configured to be free of an electrical connection with the integrated device.Type: GrantFiled: February 12, 2020Date of Patent: August 2, 2022Assignee: QUALCOMM IncorporatedInventors: David Fraser Rae, John Holmes, Marcus Hsu, Kuiwon Kang, Avantika Sodhi
-
Patent number: 11393808Abstract: Examples of semiconductor packages with stacked RDLs described herein may include, for example, a first RDL comprising multiple RDL layers coupled to a second RDL comprising multiple RDL layers using copper pillars and an underfill in place of a conventional substrate. The examples herein may use RDLs instead of substrates to achieve smaller design feature size (x, y dimensions reduction), thinner copper layers and less metal usage (z dimension reduction), flexibility to attach semiconductor dies and surface mount devices (SMD) on either side of the package, and less number of built-up RDL layers.Type: GrantFiled: October 2, 2019Date of Patent: July 19, 2022Assignee: QUALCOMM IncorporatedInventors: Aniket Patil, Hong Bok We, David Fraser Rae
-
Publication number: 20220013472Abstract: Packages are configured to include an electromagnetic interference (EMI) shield. According to one example, a package includes a substrate, an electrical component, and an EMI shield. The substrate includes a first surface and a second surface. The electrical component may be coupled to the first side of the substrate. The EMI shield is formed with at least one passive device. The at least one passive device is coupled to the first surface of the substrate. The at least one passive device is located laterally to the at least one electrical component, and extends along at least a portion of the electrical component. Other aspects, embodiments, and features are also included.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Inventors: Jeahyeong HAN, David Fraser RAE, Rajneesh KUMAR
-
Publication number: 20210351145Abstract: A package that includes a first redistribution portion, a second redistribution portion, a third redistribution portion, a first encapsulation layer coupled to the first redistribution portion and the third redistribution portion, a first discrete device encapsulated by the first encapsulation layer, wherein the first discrete device is located between the first redistribution portion and the third redistribution portion, a second encapsulation layer coupled to the first redistribution portion and the second redistribution portion, and a second discrete device encapsulated by the second encapsulation layer, wherein the second discrete device is located between the first redistribution portion and the second redistribution portion.Type: ApplicationFiled: May 6, 2020Publication date: November 11, 2021Inventors: Aniket PATIL, David Fraser RAE, Hong Bok WE
-
Publication number: 20210280523Abstract: Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die (“IC die”) module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the overall height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections.Type: ApplicationFiled: June 30, 2020Publication date: September 9, 2021Inventors: Hong Bok We, Aniket Patil, Marcus Hsu, David Fraser Rae
-
Publication number: 20210249325Abstract: A package that includes a first substrate, an integrated device coupled to the first substrate, a second substrate coupled to the integrated device, and an encapsulation layer located between the first substrate and the second substrate. The second substrate is configured to operate as a heat spreader. The second substrate is configured to be free of an electrical connection with the integrated device.Type: ApplicationFiled: February 12, 2020Publication date: August 12, 2021Inventors: David Fraser RAE, John HOLMES, Marcus HSU, Kuiwon KANG, Avantika SODHI
-
Publication number: 20210104507Abstract: Examples of semiconductor packages with stacked RDLs described herein may include, for example, a first RDL comprising multiple RDL layers coupled to a second RDL comprising multiple RDL layers using copper pillars and an underfill in place of a conventional substrate. The examples herein may use RDLs instead of substrates to achieve smaller design feature size (x, y dimensions reduction), thinner copper layers and less metal usage (z dimension reduction), flexibility to attach semiconductor dies and surface mount devices (SMD) on either side of the package, and less number of built-up RDL layers.Type: ApplicationFiled: October 2, 2019Publication date: April 8, 2021Inventors: Aniket PATIL, Hong Bok WE, David Fraser RAE
-
Publication number: 20190341352Abstract: A semiconductor package comprises a substrate, a die mounted on the substrate, and a mold formed over the die and on the substrate, the mold having a top surface and a plurality of tapered side surfaces, wherein the tapered side surfaces provide uniform thickness of an electromagnetic interference (EMI) shielding film.Type: ApplicationFiled: May 2, 2018Publication date: November 7, 2019Inventors: Hong Bok WE, Chin-Kwan KIM, Jaehyun YEON, Manuel ALDRETE, David Fraser RAE
-
Patent number: 10410971Abstract: A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.Type: GrantFiled: August 29, 2017Date of Patent: September 10, 2019Assignee: QUALCOMM IncorporatedInventors: David Fraser Rae, Hong Bok We, Christopher Healy, Chin-Kwan Kim
-
Publication number: 20190067205Abstract: A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Inventors: David Fraser RAE, Hong Bok WE, Christopher HEALY, Chin-Kwan KIM
-
Patent number: 10163687Abstract: A package may include a die proximate to a structure having a substrate with interconnects and a first component coupled to the interconnects. The die may be face up or face down. The package may include a first redistribution layer coupling the die to the interconnects of the structure and a mold compound covering the die and maybe the structure.Type: GrantFiled: September 22, 2015Date of Patent: December 25, 2018Assignee: QUALCOMM IncorporatedInventors: David Fraser Rae, Lizabeth Ann Keser, Reynante Tamunan Alvarado
-
Patent number: 9985010Abstract: An integrated package may be manufactured in a die face up orientation with a component proximate to the attached die by creating a cavity in the mold compound during fabrication. The cavity is created with an adhesive layer on the bottom to hold a component such that the top surface of the component is co-planar with the top surface of the attached die. This may allow backside grinding to take place that will not damage the component because the top surface alignment between the attached die and the component prevents the depth of the cavity from extending into the portion of the package that is ground away.Type: GrantFiled: September 20, 2015Date of Patent: May 29, 2018Assignee: QUALCOMM IncorporatedInventors: David Fraser Rae, Lizabeth Ann Keser, Reynante Tamunan Alvarado
-
Patent number: 9806048Abstract: A proposed device may reduce or eliminate a step between a die and a mold compound. Bottom and top surfaces of the die may respectively be the active and non-active sides of the die. The mold compound maybe above the top surface of the die in a fan-in area corresponding to a lateral width of the die and may also be in a fan-out area corresponding to an area that extends laterally away from a side surface of the die. The mold compound in the fan-in area need not be coplanar with the mold compound in at least a portion of the fan-out area. The device may also include a redistribution layer below the bottom surface of the die and below the mold compound, and may further include an interconnect below the redistribution layer and electrically coupled to the die through the redistribution layer. A portion of the redistribution layer may be in the fan-out area.Type: GrantFiled: March 16, 2016Date of Patent: October 31, 2017Assignee: QUALCOMM IncorporatedInventors: Lizabeth Ann Keser, David Fraser Rae, Reynante Tamunan Alvarado
-
Publication number: 20170271289Abstract: A proposed device may reduce or eliminate a step between a die and a mold compound. Bottom and top surfaces of the die may respectively be the active and non-active sides of the die. The mold compound maybe above the top surface of the die in a fan-in area corresponding to a lateral width of the die and may also be in a fan-out area corresponding to an area that extends laterally away from a side surface of the die. The mold compound in the fan-in area need not be coplanar with the mold compound in at least a portion of the fan-out area. The device may also include a redistribution layer below the bottom surface of the die and below the mold compound, and may further include an interconnect below the redistribution layer and electrically coupled to the die through the redistribution layer. A portion of the redistribution layer may be in the fan-out area.Type: ApplicationFiled: March 16, 2016Publication date: September 21, 2017Inventors: Lizabeth Ann KESER, David Fraser RAE, Reynante Tamunan ALVARADO
-
Patent number: 9679873Abstract: An integrated circuit (IC) package that includes a first die, a wire bond coupled to the first die, a first encapsulation layer that at least partially encapsulates the first die and the wire bond, a second die, a redistribution portion coupled to the second die, and a second encapsulation layer that at least partially encapsulates the second die. In some implementations, the wire bond is coupled to the redistribution portion. In some implementations, the integrated circuit (IC) package further includes a package interconnect that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package further includes a via that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package has a height of about 500 microns (?m) or less.Type: GrantFiled: July 28, 2015Date of Patent: June 13, 2017Assignee: QUALCOMM IncorporatedInventors: Lizabeth Ann Keser, David Fraser Rae, Piyush Gupta
-
Patent number: 9601435Abstract: A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.Type: GrantFiled: January 22, 2015Date of Patent: March 21, 2017Assignee: QUALCOMM IncorporatedInventors: Chin-Kwan Kim, David Fraser Rae, Rajneesh Kumar, Milind Pravin Shah, Omar James Bchir
-
Patent number: 9601472Abstract: Some features pertain to a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first integrated circuit package, and a second package coupled to the first package through the first solder interconnect. The second package includes a first die, a package interconnect comprising a first pad, where the first solder interconnect is coupled to the first pad of the package interconnect. The second package also includes a redistribution portion coupled to the first die and the package interconnect, an encapsulation layer at least partially encapsulating the first die and the package interconnect. The first pad may include a surface that has low roughness. The encapsulation layer may encapsulate the package interconnect such that the encapsulation layer encapsulates at least a portion of the first solder interconnect.Type: GrantFiled: August 27, 2015Date of Patent: March 21, 2017Assignee: QUALCOMM IncorporatedInventors: Lizabeth Ann Keser, David Fraser Rae
-
Publication number: 20160372446Abstract: An integrated circuit (IC) package that includes a first die, a wire bond coupled to the first die, a first encapsulation layer that at least partially encapsulates the first die and the wire bond, a second die, a redistribution portion coupled to the second die, and a second encapsulation layer that at least partially encapsulates the second die. In some implementations, the wire bond is coupled to the redistribution portion. In some implementations, the integrated circuit (IC) package further includes a package interconnect that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package further includes a via that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package has a height of about 500 microns (?m) or less.Type: ApplicationFiled: July 28, 2015Publication date: December 22, 2016Inventors: Lizabeth Ann Keser, David Fraser Rae, Piyush Gupta