Abstract: The invention pertains to a method and apparatus for attaching tissue to bone. Particularly, the invention relates to bone anchors for receiving (or being pre-loaded with) sutures for connecting to soft tissue that is to be attached to bone, including tools for implanting the bone anchors and facilitating the attachment of soft tissue to bone via the bone anchors and procedures for using the same.

Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.

Abstract: A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component.

Abstract: One embodiment of the invention sets forth a technique for compressing and storing display data and optionally compressing and storing cursor data in a memory that is local to a graphics processing unit to reduce the power consumed by a mobile computing device when refreshing the screen. Compressing the display data and optionally the cursor data also reduces the relative cost of the invention by reducing the size of the local memory relative to the size that would be necessary if the display data were stored locally in uncompressed form. Thus, the invention may improve mobile computing device battery life, while keeping additional costs low.

Abstract: Circuits, methods, and systems that reduce or eliminate the number of data transfers between a system memory and a graphics processor under certain conditions. After inactivity by a user of an electronic device is detected, the color fidelity of pixels being displayed is reduced. Color fidelity can be reduced by compressing pixel values, and the compression may be non-lossless, for example, pixel data bits may be truncated. The degree of compression can be progressively increased for longer durations of inactivity, and this progression may be limited by a threshold. Inactivity may be detected by a lack of input from devices such as a keyboard, pen, mouse, or other input device. Once activity is resumed, uncompressed pixel data, or pixel data that is compressed in a lossless manner, is displayed.

Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.

Abstract: Circuits, methods, and systems that reduce or eliminate the number of data transfers between a system memory and a graphics processor under certain conditions. After inactivity by a user of an electronic device is detected, the color fidelity of pixels being displayed is reduced. Color fidelity can be reduced by compressing pixel values, and the compression may be non-lossless, for example, pixel data bits may be truncated. The degree of compression can be progressively increased for longer durations of inactivity, and this progression may be limited by a threshold. Inactivity may be detected by a lack of input from devices such as a keyboard, pen, mouse, or other input device. Once activity is resumed, uncompressed pixel data, or pixel data that is compressed in a lossless manner, is displayed.

Abstract: A digital content system is disclosed. A security engine disposed in a bridge provides cryptographic services. Clear text digital data received from a central processing unit is encrypted and transferred via the bridge over unsecured data paths as cipher text.

Abstract: Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on the number of pending non-posted requests is maintained and not exceed, such that deadlock is avoided. Another exemplary embodiment provides an arbiter that tracks a number of pending posted requests. When the number pending posted requests reaches a predetermined or programmable level, a Block Peer-to-Peer signal is sent to the arbiter's clients, again avoiding deadlock.

Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.

Abstract: A method and system for implementing a generalized system stutter are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of blocking a first request received from a first of a plurality of bus masters during a low power state of a computing device for as long as permissible by the timing requirements of the computing device, wherein the first request is capable of triggering the computing device to transition out of the low power state, and during an active state of the computing device, servicing the first request along with other pending requests from the rest of the plurality of bus masters before the computing device transitions back to the low power state.

Abstract: Memory component temperature information is used to implement a method for ODT (on die termination) thermal load management. A respective temperature of a plurality of memory components are accessed, and based on this temperature, an ODT cycle is directed to a first of the memory components to avoid imposing a thermal load from the ODT cycle on a second of the memory components.

Abstract: To display a row of characters in the VGA alphanumeric mode, the ASCII and attribute bits for all such characters are retrieved from the main memory and stored in a local cache memory. The font and unused bits that are also retrieved from the memory during the retrieval of ASCII and attribute bits are discarded. The stored ASCII and attribute bits for each such character is then used to compute the address of the associated font bits in the main memory. Next, for each character, the font bits are retrieved from the main memory using a burst read operation and using the computed address for that font. The font bits associated with all the characters in the row are stored in the local cache memory and are subsequently scanned out to be used in the display of the characters.

Abstract: One embodiment of the invention sets forth a technique for compressing and storing display data and optionally compressing and storing cursor data in a memory that is local to a graphics processing unit to reduce the power consumed by a mobile computing device when refreshing the screen. Compressing the display data and optionally the cursor data also reduces the relative cost of the invention by reducing the size of the local memory relative to the size that would be necessary if the display data were stored locally in uncompressed form. Thus, the invention may improve mobile computing device battery life, while keeping additional costs low.

Abstract: A method of displaying graphics data is described. The method involves accessing the graphics data in a memory subsystem associated with one graphics subsystem. The graphics data is transmitted to a second graphics subsystem, where it is displayed on a monitor coupled to the second graphics subsystem.

Abstract: Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address and control lines of the redundant memory interface may be individually enabled and disabled. If a line in the additional interface is enabled, it and its corresponding line in the first interface drive a reduced load and may operate at the higher 1T data rate. If a line in the additional interface is disabled, then its corresponding line in the first interface drives a higher load and may operate at the slower 2T data rate. In either case, the operating speed of the interface may also be considered in determining whether each line operates with 1T or 2T timing.

Abstract: Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed circuit board design. A specific embodiment of the present invention achieves this using a single integrated circuit design where the datapath width is selected using a bonding option, fuse, data input, or other selection mechanism. The specific embodiment supports both 64 and 128-bit datapaths, though other numbers of datapaths, and other datapath widths are supported by other embodiments.

Abstract: Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address and control lines of the redundant memory interface may be individually enabled and disabled. If a line in the additional interface is enabled, it and its corresponding line in the first interface drive a reduced load and may operate at the higher 1T data rate. If a line in the additional interface is disabled, then its corresponding line in the first interface drives a higher load and may operate at the slower 2T data rate. In either case, the operating speed of the interface may also be considered in determining whether each line operates with 1T or 2T timing.

Abstract: Systems and methods for using a graphics processor to perform RAID parity functions may improve disk access performance. A method is provided for configuring a graphics processor to perform XOR parity computations when data is written to the RAID array. Another method is provided for configuring the graphics processor to perform the XOR parity computations to restore data when a disk is damaged. Using the graphics processor as a coprocessor to offload parity computations from a central processing unit may improve disk access performance and overall system performance.

Abstract: Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on the number of pending non-posted requests is maintained and not exceed, such that deadlock is avoided. Another exemplary embodiment provides an arbiter that tracks a number of pending posted requests. When the number pending posted requests reaches a predetermined or programmable level, a Block Peer-to-Peer signal is sent to the arbiter's clients, again avoiding deadlock.