Patents by Inventor David G. Springberg
David G. Springberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960735Abstract: The present disclosure includes systems, apparatuses, and methods related to memory channel controller operation. For example, a data type associated with an access request may be determined. The access request may be executed by utilizing, responsive to determining the access request is associated with a first data type, a first memory channel controller coupled to a first memory device to access a first memory address range, associated with the first data type, allocated to the first memory device. The access request may be executed by utilizing, responsive to determining the access request is associated with a second data type, the first memory channel controller and a second memory channel controller coupled to a second memory device to access a second memory address range, associated with the second data type, allocated among the first memory device and the second memory device.Type: GrantFiled: September 1, 2021Date of Patent: April 16, 2024Assignee: Micron Technology, Inc.Inventor: David G. Springberg
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Patent number: 11854637Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.Type: GrantFiled: January 31, 2023Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Michael R. Spica, David G. Springberg
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Patent number: 11829638Abstract: Described herein is a system comprising one or more external dynamic random access memory (DRAM) devices having a first programming unit buffer and a second programming unit buffer, an internal static RAM (SRAM) device, one or more non-volatile memory (NVM) devices, and a processing device, operatively coupled with the one or more external DRAM devices, the internal SRAM device, and the one or more NVM devices. The processing device transfers first write data from the first programming unit buffer to the internal SRAM device responsive to the first write data satisfying a programming unit (PU) threshold, the PU threshold pertaining to a PU of the one or more NVM devices. The processing device also writes the first write data from the internal SRAM device as a first programming unit to the one or more NVM devices, and transfers a second write data from the second programming unit buffer to the internal SRAM device responsive to the second write data satisfying the PU threshold.Type: GrantFiled: November 29, 2021Date of Patent: November 28, 2023Assignee: Micron Technology, Inc.Inventors: David G. Springberg, David Sluiter
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Publication number: 20230178163Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.Type: ApplicationFiled: January 31, 2023Publication date: June 8, 2023Inventors: Michael R. Spica, David G. Springberg
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Publication number: 20230060322Abstract: The present disclosure includes systems, apparatuses, and methods related to memory channel controller operation. For example, a data type associated with an access request may be determined. The access request may be executed by utilizing, responsive to determining the access request is associated with a first data type, a first memory channel controller coupled to a first memory device to access a first memory address range, associated with the first data type, allocated to the first memory device. The access request may be executed by utilizing, responsive to determining the access request is associated with a second data type, the first memory channel controller and a second memory channel controller coupled to a second memory device to access a second memory address range, associated with the second data type, allocated among the first memory device and the second memory device.Type: ApplicationFiled: September 1, 2021Publication date: March 2, 2023Inventor: David G. Springberg
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Patent number: 11581053Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.Type: GrantFiled: August 6, 2020Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: Michael R. Spica, David G. Springberg
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Publication number: 20220083265Abstract: Described herein is a system comprising one or more external dynamic random access memory (DRAM) devices having a first programming unit buffer and a second programming unit buffer, an internal static RAM (SRAM) device, one or more non-volatile memory (NVM) devices, and a processing device, operatively coupled with the one or more external DRAM devices, the internal SRAM device, and the one or more NVM devices. The processing device transfers first write data from the first programming unit buffer to the internal SRAM device responsive to the first write data satisfying a programming unit (PU) threshold, the PU threshold pertaining to a PU of the one or more NVM devices. The processing device also writes the first write data from the internal SRAM device as a first programming unit to the one or more NVM devices, and transfers a second write data from the second programming unit buffer to the internal SRAM device responsive to the second write data satisfying the PU threshold.Type: ApplicationFiled: November 29, 2021Publication date: March 17, 2022Inventors: David G. Springberg, David Sluiter
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Publication number: 20220044750Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.Type: ApplicationFiled: August 6, 2020Publication date: February 10, 2022Inventors: Michael R. Spica, David G. Springberg
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Patent number: 11188250Abstract: Described herein are embodiments related to a two-stage hybrid memory buffer for multiple streams in memory sub-systems. A processing device determines that first write data of a first stream stored in a host buffer component satisfies a threshold to program a first programming unit. The processing device transfers the first write data to the staging buffer component from the host buffer component, and writes the first write data from the staging buffer component as the first programming unit to a first die of multiple non-volatile memory (NVM) dies. The processing device determines that second write data of a second stream satisfies a threshold to program a second programming unit, transfers the second write data to the staging buffer component from the host buffer component, and writes the second write data from the staging buffer component as the second programming unit to a second die of the multiple NVM dies.Type: GrantFiled: October 25, 2018Date of Patent: November 30, 2021Assignee: Micron Technology, Inc.Inventors: David G. Springberg, David Sluiter
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Publication number: 20210342236Abstract: A command to transfer data in a portion of a memory component to a recovery portion of a different memory component is received from a host system, wherein the portion of the memory component is associated with a portion of the memory component that has failed, and the data in the portion of the memory component is recovered and transferred to the recovery portion of the different memory component without moving or processing the data through the host system responsive to receipt of the command.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Inventor: David G. Springberg
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Patent number: 11068365Abstract: A command to transfer data in a portion of a memory component to a recovery portion of a different memory component is received from a host system, wherein the portion of the memory component is associated with a portion of the memory component that has failed, and the data in the portion of the memory component is recovered and transferred to the recovery portion of the different memory component without moving or processing the data through the host system responsive to receipt of the command.Type: GrantFiled: August 23, 2018Date of Patent: July 20, 2021Assignee: Micron Technology, Inc.Inventor: David G. Springberg
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Publication number: 20200133563Abstract: Described herein are embodiments related to a two-stage hybrid memory buffer for multiple streams in memory sub-systems. A processing device determines that first write data of a first stream stored in a host buffer component satisfies a threshold to program a first programming unit. The processing device transfers the first write data to the staging buffer component from the host buffer component, and writes the first write data from the staging buffer component as the first programming unit to a first die of multiple non-volatile memory (NVM) dies. The processing device determines that second write data of a second stream satisfies a threshold to program a second programming unit, transfers the second write data to the staging buffer component from the host buffer component, and writes the second write data from the staging buffer component as the second programming unit to a second die of the multiple NVM dies.Type: ApplicationFiled: October 25, 2018Publication date: April 30, 2020Inventors: David G. Springberg, David Sluiter
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Publication number: 20200065204Abstract: A command to transfer data in a portion of a memory component to a recovery portion of a different memory component is received from a host system, wherein the portion of the memory component is associated with a portion of the memory component that has failed, and the data in the portion of the memory component is recovered and transferred to the recovery portion of the different memory component without moving or processing the data through the host system responsive to receipt of the command.Type: ApplicationFiled: August 23, 2018Publication date: February 27, 2020Inventor: David G. Springberg
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Patent number: 8873177Abstract: Hardware-based methods and apparatus are provided for inter-track interference mitigation in magnetic recording systems. Inter-track interference (ITI) is mitigated in a magnetic recording system by obtaining ITI cancellation data; and providing the ITI cancellation data to an ITI mitigation circuit using a write data path in the magnetic recording system. The write data path can optionally operate substantially simultaneously with the read data path performing the read operation. The ITI cancellation data comprises, for example, user data and/or media data.Type: GrantFiled: September 30, 2011Date of Patent: October 28, 2014Assignee: LSI CorporationInventors: Kurt J. Worrell, Erich F. Haratsch, Changyou Xu, Jefferson E. Singleton, Kripa Venkatachalam, David G. Springberg
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Publication number: 20130083417Abstract: Hardware-based methods and apparatus are provided for inter-track interference mitigation in magnetic recording systems. Inter-track interference (ITI) is mitigated in a magnetic recording system by obtaining ITI cancellation data; and providing the ITI cancellation data to an ITI mitigation circuit using a write data path in the magnetic recording system. The write data path can optionally operate substantially simultaneously with the read data path performing the read operation. The ITI cancellation data comprises, for example, user data and/or media data.Type: ApplicationFiled: September 30, 2011Publication date: April 4, 2013Inventors: Kurt J. Worrell, Erich F. Haratsch, Changyou Xu, Jefferson E. Singleton, Kripa Venkatachalam, David G. Springberg