Patents by Inventor David GenLong Chow
David GenLong Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7532498Abstract: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.Type: GrantFiled: November 21, 2006Date of Patent: May 12, 2009Assignee: Intel CorporationInventors: David GenLong Chow, Hans Ola Dahl, Trygve Willassen
-
Patent number: 7161825Abstract: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.Type: GrantFiled: May 9, 2005Date of Patent: January 9, 2007Assignee: Intel CorporationInventors: David GenLong Chow, Hans Ola Dahl, Trygve Willassen
-
Patent number: 7113419Abstract: A ferroelectric memory device comprises a plurality of subarrays having a plurality of bitlines and a plurality of wordlines crossing over the bitlines. Ferroelectric material is disposed between the wordlines and the bitlines to define a ferroelectric cell at each crossing of the wordlines and bitlines. Each subarray further comprises left and right voltage converters disposed on opposite sides thereof, to drive respective first and second sets of wordlines within the subarray. A plurality of global wordlines are couple to the left and right voltage converters of each subarray and are configured to establish the drive levels for respective wordlines of the subarrays. A bitline multiplexer selectively couples the bitlines of a select subarray to a plurality of sense amplifiers.Type: GrantFiled: March 21, 2005Date of Patent: September 26, 2006Assignee: Intel CorporationInventor: David GenLong Chow
-
Patent number: 7082047Abstract: A memory system. The system includes at least two ferroelectric memory devices arranged sequentially. Each memory device has a data in signal and a data out signal, and the data out signal each memory device is transmitted as the data in signal of the next device in sequence. A system controller generates an initial data in signal for the first memory device. A data bus transfers data between each memory device and the system controller and an address bus provide addressing of the memory devices.Type: GrantFiled: April 18, 2005Date of Patent: July 25, 2006Assignee: Intel CorporationInventor: David GenLong Chow
-
Patent number: 7057969Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a self-timing module to adjust timing of the integrator sensing based upon a predefined voltage level.Type: GrantFiled: April 6, 2005Date of Patent: June 6, 2006Assignee: Intel CorporationInventors: David GenLong Chow, Hans Ola Dahl
-
Patent number: 6920060Abstract: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.Type: GrantFiled: August 14, 2002Date of Patent: July 19, 2005Assignee: Intel CorporationInventors: David GenLong Chow, Hans Ola Dahl, Trygve Willassen
-
Patent number: 6914839Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a self-timing module to adjust timing of the integrator sensing based upon a predefined voltage level.Type: GrantFiled: December 24, 2001Date of Patent: July 5, 2005Assignee: Intel CorporationInventors: David GenLong Chow, Hans Ola Dahl
-
Patent number: 6901001Abstract: A memory system. The system includes at least two ferroelectric memory devices arranged sequentially. Each memory device has a data in signal and a data out signal, and the data out signal each memory device is transmitted as the data in signal of the next device in sequence. A system controller generates an initial data in signal for the first memory device. A data bus transfers data between each memory device and the system controller and an address bus provide addressing of the memory devices.Type: GrantFiled: September 4, 2003Date of Patent: May 31, 2005Assignee: Intel CorporationInventor: David GenLong Chow
-
Patent number: 6888737Abstract: A ferroelectric memory includes wordlines that cross over bitlines with a ferroelectric cell at each crossing. When reading a select cell of the array, sneak currents are drawn from an active bitline. An integration amplifier begins integrating charge propagated by the active bitline, and an active wordline receives a read level voltage. A first integration value is then obtained from the integration amplifier. Following the first integration, the integration amplifier is cleared and the voltage of the active wordline reduced to a quiescent level. Integration and wordline activation are again performed to obtain a second integration value. The second value is subtracted from the first, and the difference compared to a threshold to determine a data value.Type: GrantFiled: September 2, 2003Date of Patent: May 3, 2005Assignee: Intel CorporationInventor: David GenLong Chow
-
Patent number: 6876567Abstract: A ferroelectric memory device comprises a plurality of subarrays having a plurality of bitlines and a plurality of wordlines crossing over the bitlines. Ferroelectric material is disposed between the wordlines and the bitlines to define a ferroelectric cell at each crossing of the wordlines and bitlines. Each subarray further comprises left and right voltage converters disposed on opposite sides thereof, to drive respective first and second sets of wordlines within the subarray. A plurality of global wordlines are couple to the left and right voltage converters of each subarray and are configured to establish the drive levels for respective wordlines of the subarrays. A bitline multiplexer selectively couples the bitlines of a select subarray to a plurality of sense amplifiers.Type: GrantFiled: December 21, 2001Date of Patent: April 5, 2005Assignee: Intel CorporationInventor: David GenLong Chow
-
Patent number: 6781217Abstract: A transmission line structure comprises a plurality of conductive lines over an insulating layer. With three conductive lines, a center conductive line is disposed between the outer conductive lines to define a gap distance therebetween that is less than their height. In a further aspect, a conductive layer (e.g., a ground plane) contacts the insulating layer on a side thereof opposite the plurality of conductive lines. A ratio for the height of the conductive lines relative to the distance therebetween is kept greater than another ratio for the width of the center conductor relative to the thickness of the insulating layer.Type: GrantFiled: December 21, 2001Date of Patent: August 24, 2004Assignee: Intel CorporationInventor: David GenLong Chow
-
Publication number: 20040047212Abstract: A memory system. The system includes at least two ferroelectric memory devices arranged sequentially. Each memory device has a data in signal and a data out signal, and the data out signal each memory device is transmitted as the data in signal of the next device in sequence. A system controller generates an initial data in signal for the first memory device. A data bus transfers data between each memory device and the system controller and an address bus provide addressing of the memory devices.Type: ApplicationFiled: September 4, 2003Publication date: March 11, 2004Applicant: Intel CorporationInventor: David GenLong Chow
-
Publication number: 20040042288Abstract: A ferroelectric memory includes includes wordlines that cross over bitlines with a ferroelectric cell at each crossing. When reading a select cell of the array, sneak currents are drawn from an active bitline. An integration amplifier begins integrating charge propagated by the active bitline, and an active wordline receives a read level voltage. A first integration value is then obtained from the integration amplifier. Following the first integration, the integration amplifier is cleared and the voltage of the active wordline reduced to a quiescent level. Integration and wordline activation are again performed to obtain a second integration value. The second value is subtracted from the first, and the difference compared to a threshold to determine a data value.Type: ApplicationFiled: September 2, 2003Publication date: March 4, 2004Applicant: Intel CorporationInventor: David GenLong Chow
-
Publication number: 20040032759Abstract: A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.Type: ApplicationFiled: August 14, 2002Publication date: February 19, 2004Applicant: Intel CorporationInventors: David GenLong Chow, Hans Ola Dahl, Trygve Willassen
-
Patent number: 6667655Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a direct-timing module to time a period of integrator sensing based upon a predefined time period.Type: GrantFiled: March 14, 2003Date of Patent: December 23, 2003Assignee: Intel CorporationInventors: David GenLong Chow, Hans Ola Dahl
-
Patent number: 6646904Abstract: A ferroelectric memory includes wordlines that cross over bitlines with a ferroelectric cell at each crossing. When reading a select cell of the array, sneak currents are drawn from an active bitline. An integration amplifier begins integrating charge propagated by the active bitline, and an active wordline receives a read level voltage. A first integration value is then obtained from the integration amplifier. Following the first integration, the integration amplifier is cleared and the voltage of the active wordline reduced to a quiescent level. Integration and wordline activation are again performed to obtain a second integration value. The second value is subtracted from the first, and the difference compared to a threshold to determine a data value.Type: GrantFiled: December 21, 2001Date of Patent: November 11, 2003Assignee: Intel CorporationInventor: David GenLong Chow
-
Patent number: 6646903Abstract: A memory system. The system includes at least two ferroelectric memory devices arranged sequentially. Each memory device has a data in signal and a data out signal, and the data out signal each memory device is transmitted as the data in signal of the next device in sequence. A system controller generates an initial data in signal for the first memory device. A data bus transfers data between each memory device and the system controller and an address bus provide addressing of the memory devices.Type: GrantFiled: December 3, 2001Date of Patent: November 11, 2003Assignee: Intel CorporationInventor: David GenLong Chow
-
Publication number: 20030151452Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a direct-timing module to time a period of integrator sensing based upon a predefined time period.Type: ApplicationFiled: March 14, 2003Publication date: August 14, 2003Applicant: Intel CorporationInventors: David GenLong Chow, Hans Ola Dahl
-
Publication number: 20030120859Abstract: A ferroelectric memory device comprises a plurality of subarrays having a plurality of bitlines and a plurality of wordlines crossing over the bitlines. Ferroelectric material is disposed between the wordlines and the bitlines to define a ferroelectric cell at each crossing of the wordlines and bitlines. Each subarray further comprises left and right voltage converters disposed on opposite sides thereof, to drive respective first and second sets of wordlines within the subarray. A plurality of global wordlines are couple to the left and right voltage converters of each subarray and are configured to establish the drive levels for respective wordlines of the subarrays. A bitline multiplexer selectively couples the bitlines of a select subarray to a plurality of sense amplifiers.Type: ApplicationFiled: December 21, 2001Publication date: June 26, 2003Applicant: Intel CorporationInventor: David GenLong Chow
-
Publication number: 20030120964Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a self-timing module to adjust timing of the integrator sensing based upon a predefined voltage level.Type: ApplicationFiled: December 24, 2001Publication date: June 26, 2003Applicant: Intel CorporationInventors: David GenLong Chow, Hans Ola Dahl