Abstract: A method of forming an interconnect structure for an integrated circuit. A dielectric stack is formed on the substrate including an etch-stop layer, a low-k or ULK dielectric layer, and a hard mask layer. The low-k or ULK dielectric is etched using at least two etching processes wherein each etching process is followed by an etch repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma. The photoresist may be removed using at least two ashing processes wherein each ashing process is followed by an ash repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma.

Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

Abstract: A method of forming an interconnect structure for an integrated circuit. A dielectric stack is formed on the substrate including an etch-stop layer, a low-k or ULK dielectric layer, and a hard mask layer. The low-k or ULK dielectric is etched using at least two etching processes wherein each etching process is followed by an etch repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma. The photoresist may be removed using at least two ashing processes wherein each ashing process is followed by an ash repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma.

Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

Abstract: An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (SixBN) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity MOS transistor and the second polarity MOS transistor. The hard mask is removed from source/drain regions of the first polarity MOS transistor and left in place over the second polarity MOS transistor. Semiconductor material is epitaxially grown at the source/drain regions of the first polarity MOS transistor while the hard mask is in place. Subsequently, the hard mask is removed from the second polarity MOS transistor.

Abstract: The width of a metal contact opening is formed to be smaller than the minimum feature size of a photolithographically-defined opening. The method forms the metal contact opening by first etching the fourth layer of a multilayered hard mask structure to have a number of trenches that expose the third layer of the multilayered hard mask structure. Following this, the third, second, and first layers of the multilayered hard mask structure are selectively etched to expose uncovered regions on the top surface of an isolation layer that touches and lies over a source region and a drain region. The uncovered regions on the top surface of the isolation layer are then etched to form the metal contact openings.

Abstract: An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (SixBN) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity MOS transistor and the second polarity MOS transistor. The hard mask is removed from source/drain regions of the first polarity MOS transistor and left in place over the second polarity MOS transistor. Semiconductor material is epitaxially grown at the source/drain regions of the first polarity MOS transistor while the hard mask is in place. Subsequently, the hard mask is removed from the second polarity MOS transistor.

Abstract: The width of a metal contact opening is formed to be smaller than the minimum feature size of a photolithographically-defined opening. The method forms the metal contact opening by first etching the fourth layer of a multilayered hard mask structure to have a number of trenches that expose the third layer of the multilayered hard mask structure. Following this, the third, second, and first layers of the multilayered hard mask structure are selectively etched to expose uncovered regions on the top surface of an isolation layer that touches and lies over a source region and a drain region. The uncovered regions on the top surface of the isolation layer are then etched to form the metal contact openings.

Abstract: A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation.

Abstract: A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation.

Abstract: A method of forming a feature on a multi-layer semiconductor is disclosed. A pattern feature is formed in an uppermost layer of the multi-layer semiconductor. The multilayer semiconductor is etched with a SO2 based chemistry to extend the pattern feature to a lower layer of the multi-layer semiconductor. Use of the SO2 based chemistry for etch eliminates features roughness associated with conventional CO, SiCL4 or CO2-based chemistries.

Abstract: The disclosure provides a method of manufacturing a semiconductor device. The method comprises forming a shallow trench isolation structure, including performing a wet etch process to remove a patterned pad oxide layer located on a semiconductor substrate. The wet etch thereby produces a divot on upper lateral edges of a insulator-filled trench in the semiconductor substrate. Forming the shallow trench isolation structure also includes forming a nitride post on a vertical wall of the divot. Forming the nitride post includes depositing a nitride layer on the insulator, and dry etching the nitride layer. The dry etch is selective towards the nitride located adjacent the vertical wall such that a portion of the nitride layer remains on the vertical wall subsequent to the dry etching.

Abstract: One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

Abstract: One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

Abstract: One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

Abstract: A method and apparatus for characterizing processing operations is presented. Following exposure of a wafer to plasma, the surface charge distribution pattern on the wafer is measured. The surface charge distribution pattern on the wafer is then compared with known surface charge distribution patterns to determine if the measured charge distribution pattern correlates to desirable patterns associated with successful performance of one or more processing steps. In some embodiments, the comparison of the measured charge distribution pattern can be used to detect specific problems in one or more processing steps such that corrective action can be taken in a timely manner. The comparison between the measured charge distribution pattern and known charge distribution patterns may be performed using image comparison or using quantitative comparisons based on charge levels measured within each pattern.